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251 lines
9.6 KiB
Systemverilog
251 lines
9.6 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Prefetcher Buffer for 32 bit memory interface
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*
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* Prefetch Buffer that caches instructions. This cuts overly long critical
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* paths to the instruction cache.
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*/
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module ibex_prefetch_buffer (
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input logic clk_i,
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input logic rst_ni,
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input logic req_i,
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input logic branch_i,
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input logic [31:0] addr_i,
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input logic ready_i,
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output logic valid_o,
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output logic [31:0] rdata_o,
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output logic [31:0] addr_o,
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output logic err_o,
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// goes to instruction memory / instruction cache
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output logic instr_req_o,
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input logic instr_gnt_i,
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output logic [31:0] instr_addr_o,
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input logic [31:0] instr_rdata_i,
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input logic instr_err_i,
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input logic instr_pmp_err_i,
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input logic instr_rvalid_i,
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// Prefetch Buffer Status
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output logic busy_o
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);
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localparam int unsigned NUM_REQS = 2;
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logic valid_new_req, valid_req;
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logic valid_req_d, valid_req_q;
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logic discard_req_d, discard_req_q;
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logic gnt_or_pmp_err, rvalid_or_pmp_err;
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logic [NUM_REQS-1:0] rdata_outstanding_n, rdata_outstanding_s, rdata_outstanding_q;
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logic [NUM_REQS-1:0] branch_discard_n, branch_discard_s, branch_discard_q;
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logic [NUM_REQS-1:0] rdata_pmp_err_n, rdata_pmp_err_s, rdata_pmp_err_q;
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logic [31:0] stored_addr_d, stored_addr_q;
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logic stored_addr_en;
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logic [31:0] fetch_addr_d, fetch_addr_q;
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logic fetch_addr_en;
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logic [31:0] instr_addr, instr_addr_w_aligned;
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logic instr_or_pmp_err;
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logic fifo_valid;
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logic fifo_ready;
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logic fifo_clear;
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////////////////////////////
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// Prefetch buffer status //
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////////////////////////////
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assign busy_o = (|rdata_outstanding_q) | instr_req_o;
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//////////////////////////////////////////////
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// Fetch fifo - consumes addresses and data //
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//////////////////////////////////////////////
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// Instruction fetch errors are valid on the data phase of a request
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// PMP errors are generated in the address phase, and registered into a fake data phase
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assign instr_or_pmp_err = instr_err_i | rdata_pmp_err_q[0];
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// A branch will invalidate any previously fetched instructions.
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// Note that the FENCE.I instruction relies on this flushing behaviour on branch. If it is
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// altered the FENCE.I implementation may require changes.
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assign fifo_clear = branch_i;
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ibex_fetch_fifo #(
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.NUM_REQS (NUM_REQS)
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) fifo_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.clear_i ( fifo_clear ),
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.in_valid_i ( fifo_valid ),
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.in_addr_i ( addr_i ),
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.in_rdata_i ( instr_rdata_i ),
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.in_err_i ( instr_or_pmp_err ),
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.in_ready_o ( fifo_ready ),
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.out_valid_o ( valid_o ),
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.out_ready_i ( ready_i ),
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.out_rdata_o ( rdata_o ),
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.out_addr_o ( addr_o ),
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.out_err_o ( err_o )
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);
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//////////////
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// Requests //
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//////////////
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// Make a new request any time there is space in the FIFO, and space in the request queue
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assign valid_new_req = req_i & (fifo_ready | branch_i) & ~rdata_outstanding_q[NUM_REQS-1];
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assign valid_req = valid_req_q | valid_new_req;
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// If a request address triggers a PMP error, the external bus request is suppressed. We might
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// therefore never receive a grant for such a request. The grant is faked in this case to make
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// sure the request proceeds and the error is pushed to the FIFO.
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assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i;
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// As with the grant, the rvalid must be faked for a PMP error, since the request was suppressed.
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assign rvalid_or_pmp_err = rdata_outstanding_q[0] & (instr_rvalid_i | rdata_pmp_err_q[0]);
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// Hold the request stable for requests that didn't get granted
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assign valid_req_d = valid_req & ~gnt_or_pmp_err;
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// Record whether an outstanding bus request is cancelled by a branch
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assign discard_req_d = valid_req_q & (branch_i | discard_req_q);
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////////////////
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// Fetch addr //
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////////////////
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// Two addresses are tracked in the prefetch buffer:
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// 1. stored_addr_q - This is the address issued on the bus. It stays stable until
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// the request is granted.
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// 2. fetch_addr_q - This is our next address to fetch from. It is updated on branches to
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// capture the new address, and then for each new request issued.
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// A third address is tracked in the fetch FIFO itself:
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// 3. instr_addr_q - This is the address at the head of the FIFO, efectively our oldest fetched
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// address. This address is updated on branches, and does its own increment
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// each time the FIFO is popped.
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// 1. stored_addr_q
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// Only update stored_addr_q for new ungranted requests
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assign stored_addr_en = valid_new_req & ~valid_req_q & ~gnt_or_pmp_err;
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// Store whatever address was issued on the bus
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assign stored_addr_d = instr_addr;
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// CPU resets with a branch, so no need to reset these addresses
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always_ff @(posedge clk_i) begin
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if (stored_addr_en) begin
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stored_addr_q <= stored_addr_d;
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end
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end
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// 2. fetch_addr_q
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// Update on a branch or as soon as a request is issued
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assign fetch_addr_en = branch_i | (valid_new_req & ~valid_req_q);
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assign fetch_addr_d = (branch_i ? addr_i :
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{fetch_addr_q[31:2], 2'b00}) +
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// Current address + 4
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{{29{1'b0}},(valid_new_req & ~valid_req_q),2'b00};
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always_ff @(posedge clk_i) begin
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if (fetch_addr_en) begin
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fetch_addr_q <= fetch_addr_d;
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end
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end
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// Address mux
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assign instr_addr = valid_req_q ? stored_addr_q :
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branch_i ? addr_i :
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fetch_addr_q;
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assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00};
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///////////////////////////////
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// Request outstanding queue //
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///////////////////////////////
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for (genvar i = 0; i < NUM_REQS; i++) begin : g_outstanding_reqs
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// Request 0 (always the oldest outstanding request)
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if (i == 0) begin : g_req0
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// A request becomes outstanding once granted, and is cleared once the rvalid is received.
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// Outstanding requests shift down the queue towards entry 0.
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assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err) |
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rdata_outstanding_q[i];
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// If a branch is received at any point while a request is outstanding, it must be tracked
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// to ensure we discard the data once received
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assign branch_discard_n[i] = (valid_req & gnt_or_pmp_err & discard_req_d) |
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(branch_i & rdata_outstanding_q[i]) | branch_discard_q[i];
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// Record whether this request received a PMP error
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assign rdata_pmp_err_n[i] = (valid_req & ~rdata_outstanding_q[i] & instr_pmp_err_i) |
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rdata_pmp_err_q[i];
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end else begin : g_reqtop
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// Entries > 0 consider the FIFO fill state to calculate their next state (by checking
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// whether the previous entry is valid)
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assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err &
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rdata_outstanding_q[i-1]) |
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rdata_outstanding_q[i];
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assign branch_discard_n[i] = (valid_req & gnt_or_pmp_err & discard_req_d &
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rdata_outstanding_q[i-1]) |
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(branch_i & rdata_outstanding_q[i]) | branch_discard_q[i];
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assign rdata_pmp_err_n[i] = (valid_req & ~rdata_outstanding_q[i] & instr_pmp_err_i &
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rdata_outstanding_q[i-1]) |
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rdata_pmp_err_q[i];
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end
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end
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// Shift the entries down on each instr_rvalid_i
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assign rdata_outstanding_s = rvalid_or_pmp_err ? {1'b0,rdata_outstanding_n[NUM_REQS-1:1]} :
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rdata_outstanding_n;
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assign branch_discard_s = rvalid_or_pmp_err ? {1'b0,branch_discard_n[NUM_REQS-1:1]} :
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branch_discard_n;
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assign rdata_pmp_err_s = rvalid_or_pmp_err ? {1'b0,rdata_pmp_err_n[NUM_REQS-1:1]} :
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rdata_pmp_err_n;
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// Push a new entry to the FIFO once complete (and not cancelled by a branch)
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assign fifo_valid = rvalid_or_pmp_err & ~branch_discard_q[0];
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///////////////
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// Registers //
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///////////////
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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valid_req_q <= 1'b0;
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discard_req_q <= 1'b0;
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rdata_outstanding_q <= 'b0;
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branch_discard_q <= 'b0;
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rdata_pmp_err_q <= 'b0;
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end else begin
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valid_req_q <= valid_req_d;
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discard_req_q <= discard_req_d;
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rdata_outstanding_q <= rdata_outstanding_s;
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branch_discard_q <= branch_discard_s;
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rdata_pmp_err_q <= rdata_pmp_err_s;
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end
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end
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/////////////
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// Outputs //
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/////////////
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assign instr_req_o = valid_req;
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assign instr_addr_o = instr_addr_w_aligned;
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endmodule
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