mirror of
https://github.com/openhwgroup/cve2.git
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86979e603f
This commit adds a separate memory ports for instruction and data
fetches to the Simple System example.
* Add Dual-Port RAM with 1 cycle read/write delay, 32 bit words.
* Introduce parametric signal width definitions for bus implementation
to work with a single host / device.
* Modify Simple System top module to instantiate the new dual-port RAM.
24 lines
584 B
Text
24 lines
584 B
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:sim_shared"
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description: "Collection of useful RTL for building simulations"
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filesets:
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files_sim_sv:
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depend:
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- lowrisc:prim:assert
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files:
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- ./rtl/prim_clock_gating.sv
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- ./rtl/ram_1p.sv
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- ./rtl/ram_2p.sv
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- ./rtl/bus.sv
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- ./rtl/sim/simulator_ctrl.sv
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- ./rtl/timer.sv
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file_type: systemVerilogSource
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targets:
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default:
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filesets:
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- files_sim_sv
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