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c7cb958f0d
Update code from upstream repository https://github.com/lowRISC/opentitan to revision ca950b43a0e9ef5013b8e2e5de765bc34fb59b74 Two updates to the Ibex code were required: * Adjust the prim_secded port names to match the changes in OpenTitan. * Replace `has_ral` in `ibex_icache_env_cfg.sv` and `ibex_icache_base_test.sv` with its newer equivalent, matching https://github.com/lowRISC/opentitan/pull/5932 and the additional updates in https://github.com/lowRISC/opentitan/pull/5951. Upstream changes include: * [prim_secded] Use _i/_o suffix for port names (Philipp Wagner) * [tl,dv] Allow bits to be set in responses regardless of mask (Rupert Swarbrick) * [push_pull agent] Driver code refactor (Srikrishna Iyer) * [dv/dvsim] Group failures per test in buckets (Guillermo Maturana) * [dv/uvmdvgen] Flag error for paths in block name (Guillermo Maturana) * [prim_fifo_async] Style fixes (Philipp Wagner) * Remove non-ASCII characters from SV code and meson.build (Rupert Swarbrick) * [dv/spi_device] Fix spi_device_csr_wr_with_rand_reset timeout issue (Cindy Chen) * [otp] Update to match latest foundry wrapper (Timothy Chen) * [flash] update to match latest foundry wrapper (Timothy Chen) * [top] Latest ast integration (Timothy Chen) * [lint] Strengthen Verible lint check to 100-character lines (Rupert Swarbrick) * [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo (Martin Lueker-Boden) * [dv/otp_ctrl] Add coverage exclusions (Cindy Chen) * [dv/dvsim] Add "^Error:" as a run fail pattern. (Guillermo Maturana) * [dvsim] Fix column bug in DV summary report (Srikrishna Iyer) * [dvsim] Fix testplan test counts (Srikrishna Iyer) * [dvsim] Fix lowRISC/opentitan#6061 (Srikrishna Iyer) * [prim_clock_div] Update waiver (Michael Schaffner) * [fpv] dvsim script error (Cindy Chen) * [prim_otp] Update interface (Michael Schaffner) * [dvsim] update edacloudlauncher imports (Udi Jonnalagadda) * [dv/doc] Minor fix on dv_doc (Cindy Chen) * [dvsim] Scheduler updates - max_parallel, max_poll (Srikrishna Iyer) * [dvsim] Set `Deploy.job_name` more robustly (Srikrishna Iyer) * [prim] Make SECDED prim generation deterministic (Rupert Swarbrick) * [tool, xcel] Support dumpping the array of struct in shm/vcd (Tung Hoang) * [dv/otp_ctrl] OTP_CTRL DV doc (Cindy Chen) * [dv/dv_macros] Fix DV_PRINT_ARR_CONTENTS (Guillermo Maturana) * [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner) * [prim_usb_diff] Minor lint fix (Michael Schaffner) * [prim_clock_div] Update waiver file (Michael Schaffner) * [top] change prim_generic usage into prim (Timothy Chen) * [formal/conn] Support dvsim to publish regression result summary (Cindy Chen) * Add formatting changes from allow list (Rafal Kapuscik) * [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin Vogel) * [prim] Add Width parameter to buffer primitives (Pirmin Vogel) * [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin Vogel) * [prim] Remove temporary workaround in parameter list related to primgen (Pirmin Vogel) * [dv/dvsim] Provides more context on some failures. (Guillermo Maturana) * [dvsim] Fix local run error. (Eunchan Kim) * [dv] Support multi-ral (part 4) (Weicai Yang) * [dv/dvsim] Adds failure bucketizer for triage. (Guillermo Maturana) * [lint/docs] Update ascentlint dvsim command in readme (Michael Schaffner) * [top] Various top level lint fixes (Timothy Chen) * [pinmux/padring] Wire up the pad attribute WARL behavior modules (Michael Schaffner) * [dv] Fix tl_error failure (Weicai Yang) * [pinout] Update flash test mode and voltage signals/pads (Michael Schaffner) * [pad_wrapper] Extend the generic and Xilinx pad wrapper models (Michael Schaffner) * [dv] Update scb for all blocks (Weicai Yang) * [dv] Support multi-ral (part 3) (Weicai Yang) * [prim_arbiter,lint] Tell Verilator to split variables for scheduling (Rupert Swarbrick) * [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin Vogel) * [dvsim] Scratch root default to $REPO_TOP/scratch (Srikrishna Iyer) * [dv] Update `process_tl_access` args for all blocks (Weicai Yang) * [dv] Support multi-ral (part 2) (Weicai Yang) * [formal] Clean up some formal warnings (Cindy Chen) * [topgen] Rework pinmux datastructure and templatize tops (Michael Schaffner) * [otp_ctrl] Several small lint fixes (Michael Schaffner) * [prim_fifo_async] Make async FIFO output zero when empty (Noah Moroze) * [flash] Improve flash ECC handling based on transasction attribute (Timothy Chen) * [dv] Remove toggle coverage excl for a_user/d_user (Weicai Yang) * [dvsim] Fix remaining comments from lowRISC/opentitan#5876 (Srikrishna Iyer) * [dv] Support multi-ral (part 1) (Weicai Yang) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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| .. | ||
| ibex_alu.sv | ||
| ibex_branch_predict.sv | ||
| ibex_compressed_decoder.sv | ||
| ibex_controller.sv | ||
| ibex_core.f | ||
| ibex_core.sv | ||
| ibex_counter.sv | ||
| ibex_cs_registers.sv | ||
| ibex_csr.sv | ||
| ibex_decoder.sv | ||
| ibex_dummy_instr.sv | ||
| ibex_ex_block.sv | ||
| ibex_fetch_fifo.sv | ||
| ibex_icache.sv | ||
| ibex_id_stage.sv | ||
| ibex_if_stage.sv | ||
| ibex_load_store_unit.sv | ||
| ibex_lockstep.sv | ||
| ibex_multdiv_fast.sv | ||
| ibex_multdiv_slow.sv | ||
| ibex_pkg.sv | ||
| ibex_pmp.sv | ||
| ibex_prefetch_buffer.sv | ||
| ibex_register_file_ff.sv | ||
| ibex_register_file_fpga.sv | ||
| ibex_register_file_latch.sv | ||
| ibex_top.sv | ||
| ibex_top_tracing.sv | ||
| ibex_tracer.sv | ||
| ibex_tracer_pkg.sv | ||
| ibex_wb_stage.sv | ||