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c054a63c3d
- Add parameters and actual instantiation of icache - Add a custom CSR in the M-mode custom RW range to enable the cache - Wire up the cache invalidation signal to trigger on fence.i Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
74 lines
4.7 KiB
ReStructuredText
74 lines
4.7 KiB
ReStructuredText
.. _instruction-fetch:
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Instruction Fetch
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=================
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:file:`rtl/ibex_if_stage.sv.`
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.. figure:: images/if_stage.svg
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:name: if_stage
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:align: center
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Instruction Fetch (IF) stage
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The Instruction Fetch (IF) stage of the core is able to supply one instruction to the Instruction-Decode (ID) stage per cycle if the instruction cache or the instruction memory is able to serve one instruction per cycle.
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Instructions are fetched into a prefetch buffer (:file:`rtl/ibex_prefetch_buffer.sv`) for optimal performance and timing closure reasons.
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This buffer simply fetches instructions linearly until it is full.
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The instructions themselves are stored along with the Program Counter (PC) they came from in the fetch FIFO (:file:`rtl/ibex_fetch_fifo.sv`).
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The fetch FIFO has a feedthrough path so when empty a new instruction entering the FIFO is immediately made available on the FIFO output.
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A localparam ``DEPTH`` gives a configurable depth which is set to 3 by default.
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The top-level of the instruction fetch controls the prefetch buffer (in particular flushing it on branches/jumps/exception and beginning prefetching from the appropriate new PC) and supplies new instructions to the ID/EX stage along with their PC.
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Compressed instructions are expanded by the IF stage so the decoder can always deal with uncompressed instructions (the ID stage still receives the compressed instruction for placing into ``mtval`` on an illegal instruction exception).
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If Ibex has been configured with an instruction cache (parameter ICache == 1), then the prefetch buffer is replaced by the icache module (:ref:`icache`).
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The interfaces of the icache module are the same as the prefetch buffer with two additions.
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Firstly, a signal to enable the cache which is driven from a custom CSR.
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Secondly a signal to the flush the cache which is set every time a ``fence.i`` instruction is executed.
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Instruction-Side Memory Interface
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---------------------------------
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The following table describes the signals that are used to fetch instructions.
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This interface is a simplified version of the interface used on the data interface as described in :ref:`load-store-unit`.
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The main difference is that the instruction interface does not allow for write transactions and thus needs less signals.
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.. tabularcolumns:: |p{4cm}|l|p{9cm}|
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+-------------------------+-----------+-----------------------------------------------+
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| Signal | Direction | Description |
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+=========================+===========+===============================================+
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| ``instr_req_o`` | output | Request valid, must stay high until |
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| | | ``instr_gnt_i`` is high for one cycle |
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+-------------------------+-----------+-----------------------------------------------+
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| ``instr_addr_o[31:0]`` | output | Address, word aligned |
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+-------------------------+-----------+-----------------------------------------------+
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| ``instr_gnt_i`` | input | The other side accepted the request. |
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| | | ``instr_req_o`` may be deasserted in the next |
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| | | cycle. |
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+-------------------------+-----------+-----------------------------------------------+
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| ``instr_rvalid_i`` | input | ``instr_rdata_i`` holds valid data when |
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| | | ``instr_rvalid_i`` is high. This signal will |
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| | | be high for exactly one cycle per request. |
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+-------------------------+-----------+-----------------------------------------------+
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| ``instr_rdata_i[31:0]`` | input | Data read from memory |
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+-------------------------+-----------+-----------------------------------------------+
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| ``instr_err_i`` | input | Memory access error |
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+-------------------------+-----------+-----------------------------------------------+
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Misaligned Accesses
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-------------------
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Externally, the IF interface performs word-aligned instruction fetches only.
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Misaligned instruction fetches are handled by performing two separate word-aligned instruction fetches.
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Internally, the core can deal with both word- and half-word-aligned instruction addresses to support compressed instructions.
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The LSB of the instruction address is ignored internally.
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Protocol
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--------
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The protocol used to communicate with the instruction cache or the instruction memory is very similar to the protocol used by the LSU on the data interface of Ibex.
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See the description of the LSU in :ref:`LSU Protocol<lsu-protocol>` for details about this protocol.
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