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1aa4d5a32b
This commit contains some final optimizations regarding the bit
manipulation extension as well as the parametrization into a balanced
version and a full performance version.
Balanced Version:
* Supports ZBB, ZBS, ZBF and ZBT extensions
* Dual cycle instructions:
ror[i], rol, cmov, cmix fsl, fsr[i]
* Everything else completes in a single cycle.
Full Version:
* Supports all 32b sub extensions.
* Dual cycle instructions:
ror[i], rol, cmov, cmix fsl, fsr[i], crc32[c], bext, bdep
* Everything else completes in a single cycle.
Notable Changes:
* bext/bdep are now multi-cycle: Sharing additional register
with multiplier module
* grev/gorc instructions are implemented in separate structures
rather than sharing the shifter or butterfly network.
* Speed up decision on using rs1 or rs3 for alu_operand_a by
introducing single-bit register, to identify ternary
instructions in their first cycle.
* Introduce enumerated parameter to chose bit manipulation
implementation
Signed-off-by: ganoam <gnoam@live.com>
167 lines
9.4 KiB
ReStructuredText
167 lines
9.4 KiB
ReStructuredText
.. _instruction-decode-execute:
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Instruction Decode and Execute
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==============================
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.. figure:: images/de_ex_stage.svg
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:name: de_ex_stage
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:align: center
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Instruction Decode and Execute
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The Instruction Decode and Execute stage takes instruction data from the instruction fetch stage (which has been converted to the uncompressed representation in the compressed instruction case).
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The instructions are decoded and executed all within one cycle including the register read and write.
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The stage is made up of multiple sub-blocks which are described below.
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Instruction Decode Block (ID)
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-----------------------------
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Source File: :file:`rtl/ibex_id_stage.sv`
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The Instruction Decode (ID) controls the overall decode/execution process.
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It contains the muxes to choose what is sent to the ALU inputs and where the write data for the register file comes from.
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A small state machine is used to control multi-cycle instructions (see :ref:`pipeline-details` for more details), which stalls the whole stage whilst a multi-cycle instruction is executing.
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Controller
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----------
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Source File: :file:`rtl/ibex_controller.sv`
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The Controller contains the state machine that controls the overall execution of the processor.
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It is responsible for:
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* Handling core startup from reset
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* Setting the PC for the IF stage on jump/branch
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* Dealing with exceptions/interrupts (jump to appropriate PC, set relevant CSR values)
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* Controlling sleep/wakeup on WFI
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* Debugging control
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Decoder
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-------
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Source File: :file:`rtl/ibex_decoder.sv`
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The decoder takes uncompressed instruction data and issues appropriate control signals to the other blocks to execute the instruction.
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Register File
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-------------
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Source Files: :file:`rtl/ibex_register_file_ff.sv` :file:`rtl/ibex_register_file_latch.sv`
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See :ref:`register-file` for more details.
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Execute Block
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-------------
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Source File: :file:`rtl/ibex_ex_block.sv`
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The execute block contains the ALU and the multiplier/divider blocks, it does little beyond wiring and instantiating these blocks.
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Arithmetic Logic Unit (ALU)
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---------------------------
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Source File: :file:`rtl/ibex_alu.sv`
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The Arithmetic Logic Logic (ALU) is a purely combinational block that implements operations required for the Integer Computational Instructions and the comparison operations required for the Control Transfer Instructions in the RV32I RISC-V Specification.
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Other blocks use the ALU for the following tasks:
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* Mult/Div uses it to perform addition as part of the multiplication and division algorithms
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* It computes branch targets with a PC + Imm calculation
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* It computes memory addresses for loads and stores with a Reg + Imm calculation
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* The LSU uses it to increment addresses when performing two accesses to handle an unaligned access
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Bit Manipulation Extension
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Support for the `RISC-V Bit Manipulation Extension (Document Version 0.92, November 8, 2019) <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf>`_ is enabled via the enumerated parameter ``RV32B`` defined in :file:`rtl/ibex_pkg.sv`.
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This feature is *Experimental*.
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There are two versions of the bit manipulation extension available:
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The balanced implementation comprises a set of sub-extensions aiming for good benefits at a reasonable area overhead.
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The full implementation comprises all 32 bit instructions defined in the extension.
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The following table lists the implemented instructions in each version.
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Multi-cycle instructions are completed in 2 cycles.
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All remaining instructions complete in a single cycle.
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+---------------------------+---------------+--------------------------+
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| Z-Extension | Version | Multi-Cycle Instructions |
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+===========================+===============+==========================+
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| Zbb (Base) | Balanced/Full | rol, ror[i] |
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+---------------------------+---------------+--------------------------+
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| Zbs (Single-bit) | Balanced/Full | None |
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+---------------------------+---------------+--------------------------+
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| Zbp (Permutation) | Full | None |
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+---------------------------+---------------+--------------------------+
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| Zbp (Bit extract/deposit) | Full | All |
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+---------------------------+---------------+--------------------------+
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| Zbf (Bit-field place) | Balanced/Full | All |
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+---------------------------+---------------+--------------------------+
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| Zbc (Carry-less multiply) | Full | None |
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+---------------------------+---------------+--------------------------+
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| Zbr (Crc) | Full | All |
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+---------------------------+---------------+--------------------------+
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| Zbt (Ternary) | Balanced/Full | All |
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+---------------------------+---------------+--------------------------+
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| Zb_tmp (Temporary)* | Balanced/Full | None |
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+---------------------------+---------------+--------------------------+
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* The sign-extend instructions `sext.b/sext.h` are defined but not yet classified in version 0.92 of the extension proposal.
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Temporarily, they are assigned a separate Z-extension.
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The implementation of the B-extension comes with an area overhead of 1.8 to 3.0 kGE for the balanced version and 6.0 to 8.7 kGE for the full version.
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That corresponds to an approximate percentage increase in area of 9 to 14 % and 25 to 30 % for the balanced and full versions respectively.
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The ranges correspond to synthesis results generated using relaxed and maximum frequency targets respectively.
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The designs have been synthesized using Synopsys Design Compiler targeting TSMC 65 nm technology.
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.. _mult-div:
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Multiplier/Divider Block (MULT/DIV)
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-----------------------------------
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Source Files: :file:`rtl/ibex_multdiv_slow.sv` :file:`rtl/ibex_multdiv_fast.sv`
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The Multiplier/Divider (MULT/DIV) is a state machine driven block to perform multiplication and division.
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The fast and slow versions differ in multiplier only. All versions implement the same form of long division algorithm. The ALU block is used by the long division algorithm in all versions.
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Multiplier
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The multiplier can be implemented in three variants controlled via the parameter ``MultiplierImplementation``.
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Single-Cycle Multiplier
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This implementation is chosen by setting the ``MultiplierImplementation`` parameter to "single-cycle". The single-cycle multiplier makes use of three parallel multiplier units, designed to be mapped to hardware multiplier primitives on FPGAs. It is therefore the **first choice for FPGA synthesis**.
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- Using three parallel 17-bit x 17-bit multiplication units and a 34-bit accumulator, it completes a MUL instruction in 1 cycle. MULH is completed in 2 cycles.
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- This MAC is internal to the mult/div block (no external ALU use).
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- Beware it is simply implemented with the ``*`` and ``+`` operators so results heavily depend upon the synthesis tool used.
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- ASIC synthesis has not yet been tested but is expected to consume 3-4x the area of the fast multiplier for ASIC.
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Fast Multi-Cycle Multiplier
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This implementation is chosen by setting the ``MultiplierImplementation`` parameter to "fast". The fast multi-cycle multiplier provides a reasonable trade-off between area and performance. It is the **first choice for ASIC synthesis**.
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- Completes multiply in 3-4 cycles using a MAC (multiply accumulate) which is capable of a 17-bit x 17-bit multiplication with a 34-bit accumulator.
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- A MUL instruction takes 3 cycles, MULH takes 4.
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- This MAC is internal to the mult/div block (no external ALU use).
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- Beware it is simply implemented with the ``*`` and ``+`` operators so results heavily depend upon the synthesis tool used.
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- In some cases it may be desirable to replace this with a specific implementation such as an explicit gate level implementation.
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Slow Multi-Cycle Multiplier
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To select the slow multi-cycle multiplier, set the ``MultiplierImplementation`` parameter to "slow".
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- Completes multiply in clog2(``op_b``) + 1 cycles (for MUL) or 33 cycles (for MULH) using a Baugh-Wooley multiplier.
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- The ALU block is used to compute additions.
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Divider
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Both the fast and slow blocks use the same long division algorithm, it takes 37 cycles to compute (though only requires 2 cycles when there is a divide by 0) and proceeds as follows:
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- Cycle 0: Check for divide by 0
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- Cycle 1: Compute absolute value of operand A (or return result on divide by 0)
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- Cycle 2: Compute absolute value of operand B
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- Cycles 4 - 36: Perform long division as described here: https://en.wikipedia.org/wiki/Division_algorithm#Integer_division_(unsigned)_with_remainder.
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Control and Status Register Block (CSR)
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---------------------------------------
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Source File: :file:`rtl/ibex_cs_registers.sv`
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The CSR contains all of the CSRs (control/status registers).
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Any CSR read/write is handled through this block.
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Performance counters are held in this block and incremented when appropriate (this includes ``mcycle`` and ``minstret``).
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Read data from a CSR is available the same cycle it is requested.
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Further detail on the implemented CSRs can be found in :ref:`cs-registers`
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Load-Store Unit (LSU)
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---------------------
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Source File: :file:`rtl/ibex_load_store_unit.sv`
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The Load-Store Unit (LSU) interfaces with main memory to perform load and store operations.
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See :ref:`load-store-unit` for more details.
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