2c75c2b2ec
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 1ae03937f0bb4b146bb6e736bccb4821bfda556b * [prim/fifo_async] Add assertions on pointers (Tom Roberts) * [prim/fifo_async] Add support for Depth <= 2 (Tom Roberts) * [prim/fifo_async] Code tidy-up (Tom Roberts) * [top / ast] Continued ast integration (Timothy Chen) * [dvsim] Use bash when running make underneath (Srikrishna Iyer) * [prim] Increase maximum width for prim_util_memload to 312 (Greg Chadwick) * [sram_ctrl] Fix potential back-to-back partial write bug (Michael Schaffner) * [dvsim] Fix for lowRISC/opentitan#5527 (Srikrishna Iyer) * [lint] Waive Verilator UNUSED warnings for packages (Rupert Swarbrick) * [uvmdvgen] Update DV doc path and terminology (Srikrishna Iyer) * [clkmgr] Fix dft issues (Timothy Chen) * [util] add `dec` types to prim_secded_pkg (Udi Jonnalagadda) * [util] minor updates to secded_gen (Udi Jonnalagadda) * [lint] Fix a bunch of lint warnings related to long lines (>100 chars) (Michael Schaffner) * [dv] Update common intr_test seq (Weicai Yang) * [util] Slight refactor of secded_gen.py (Timothy Chen) * [tlul] Add memory transmission integrity checks (Timothy Chen) * [dvsim] Move clean_odirs to `util.py` (Srikrishna Iyer) * [dvsim] Split Deploy into Deploy and Launcher (Srikrishna Iyer) * [dvsim] Add utils.TS_FORMAT* vars (Srikrishna Iyer) * [dv/lock_reg] Update IPs to adopt the lock_reg changes (Cindy Chen) * [dv/enable_regs] Support enable registers have more than one field (Cindy Chen) * [dv/base_reg] use m_field instead of accessing field (Cindy Chen) * [dv/sram] add SRAM scrambling model for DV (Udi Jonnalagadda) * [dv/tools] Updated Coverage flow for xcelium (Rasmus Madsen) Signed-off-by: Tom Roberts <tomroberts@lowrisc.org> |
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| README.md | ||
| top_artya7.core | ||
Ibex RISC-V Core SoC Example
Please see examples for a description of this example.
Requirements
Tools
- RV32 compiler
- srecord
fusesocand its dependencies- Xilinx Vivado
Hardware
- Either a Digilent Arty A7-35 oder A7-100 board
Build
The easiest way to build and execute this example is to call the following make goals from the root directory.
Use the following for the Arty A7-35
make build-arty-35 program-arty
and for the Arty A7-100
make build-arty-100 program-arty
Software
First the software must be built. Go into examples/sw/led and call:
make CC=/path/to/RISC-V-compiler
The setting of CC is only required if riscv32-unknown-elf-gcc is not available through the PATH environment variable.
The path to the RV32 compiler /path/to/RISC-V-compiler depends on the environment.
For example, it can be for example /opt/riscv/bin/riscv-none-embed-gcc if the whole path is required or simply the name of the executable if it is available through the PATH environment variable.
This should produce a led.vmem file which is used in the synthesis to update the SRAM storage.
Hardware
Run either of the following commands at the top level to build the respective hardware.
Both variants of the Arty A7 are supported and can be selected via the --parts parameter.
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a35ticsg324-1L
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1
This will create a directory build which contains the output files, including
the bitstream.
Program
After the board is connected to the computer it can be programmed with:
fusesoc --cores-root=. run --target=synth --run lowrisc:ibex:top_artya7
LED1/LED3 and LED0/LED2 should alternately be on after the FPGA programming is finished.