Tom Roberts 2c75c2b2ec Update lowrisc_ip to lowRISC/opentitan@1ae03937f ... Update code from upstream repository https://github.com/lowRISC/opentitan to revision 1ae03937f0bb4b146bb6e736bccb4821bfda556b * [prim/fifo_async] Add assertions on pointers (Tom Roberts) * [prim/fifo_async] Add support for Depth <= 2 (Tom Roberts) * [prim/fifo_async] Code tidy-up (Tom Roberts) * [top / ast] Continued ast integration (Timothy Chen) * [dvsim] Use bash when running make underneath (Srikrishna Iyer) * [prim] Increase maximum width for prim_util_memload to 312 (Greg Chadwick) * [sram_ctrl] Fix potential back-to-back partial write bug (Michael Schaffner) * [dvsim] Fix for lowRISC/opentitan#5527 (Srikrishna Iyer) * [lint] Waive Verilator UNUSED warnings for packages (Rupert Swarbrick) * [uvmdvgen] Update DV doc path and terminology (Srikrishna Iyer) * [clkmgr] Fix dft issues (Timothy Chen) * [util] add `dec` types to prim_secded_pkg (Udi Jonnalagadda) * [util] minor updates to secded_gen (Udi Jonnalagadda) * [lint] Fix a bunch of lint warnings related to long lines (>100 chars) (Michael Schaffner) * [dv] Update common intr_test seq (Weicai Yang) * [util] Slight refactor of secded_gen.py (Timothy Chen) * [tlul] Add memory transmission integrity checks (Timothy Chen) * [dvsim] Move clean_odirs to `util.py` (Srikrishna Iyer) * [dvsim] Split Deploy into Deploy and Launcher (Srikrishna Iyer) * [dvsim] Add utils.TS_FORMAT* vars (Srikrishna Iyer) * [dv/lock_reg] Update IPs to adopt the lock_reg changes (Cindy Chen) * [dv/enable_regs] Support enable registers have more than one field (Cindy Chen) * [dv/base_reg] use m_field instead of accessing field (Cindy Chen) * [dv/sram] add SRAM scrambling model for DV (Udi Jonnalagadda) * [dv/tools] Updated Coverage flow for xcelium (Rasmus Madsen) Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>		2021-03-12 16:15:22 +00:00
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eembc_coremark	Update eembc_coremark to eembc/coremark@0c91314	2020-03-09 14:41:40 +00:00
google_riscv-dv	Update google_riscv-dv to google/riscv-dv@0b62525	2021-02-04 08:37:00 +00:00
lowrisc_ip	Update lowrisc_ip to lowRISC/opentitan@1ae03937f	2021-03-12 16:15:22 +00:00
patches	[vendor] Remove fcov patch from dv_utils	2021-03-04 09:56:36 +00:00
eembc_coremark.lock.hjson	Update eembc_coremark to eembc/coremark@0c91314	2020-03-09 14:41:40 +00:00
google_riscv-dv.lock.hjson	Update google_riscv-dv to google/riscv-dv@0b62525	2021-02-04 08:37:00 +00:00
google_riscv-dv.vendor.hjson	[dv] Add RISCV-DV patch to fix csr_test	2021-02-04 08:37:00 +00:00
lowrisc_ip.lock.hjson	Update lowrisc_ip to lowRISC/opentitan@1ae03937f	2021-03-12 16:15:22 +00:00
lowrisc_ip.vendor.hjson	Update lowrisc_ip to lowRISC/opentitan@c277e3a8	2021-01-07 18:03:44 +00:00