Greg Chadwick 7cee76bf05 [dv] Reorder checks in sim.py ... The UVM log should be checked for failures before attempting to process the core trace log. A simulation failure could mean the trace log doesn't exist and is is preferable to report the simulation error from the log rather than trace not found as a failure cause.		2021-02-15 17:52:35 +00:00
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cs_registers	[dv] Add ePMP support to cs_registers testbench	2021-02-01 12:22:49 +00:00
fcov	[dv] Ibex uarch functional coverage	2021-01-22 11:12:08 +00:00
riscv_compliance	[rtl] Avoid latch creation	2021-01-11 16:20:33 +01:00
uvm	[dv] Reorder checks in sim.py	2021-02-15 17:52:35 +00:00
verilator/pcount	Spelling fix: seperate -> separate	2020-06-05 11:37:37 +01:00