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This implemements the RISC-V Trusted Execution Environment (TEE) working group proposal 'PMP Enhancements for memory access and execution prevention on Machine mode'. The proposal is awaiting ratification and is not expected to change beyond minor tweaks before it becomes part of the RISC-V priviledged specification. No seperate 'classic' PMP only mode is provided as different PMP behaviour only occurs when the MSECCFG CSR is written to. This CSR is introduced by the proposal and has no specified function in the current RISC-V priviledged specification. |
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| .. | ||
| ibex_alu.sv | ||
| ibex_branch_predict.sv | ||
| ibex_compressed_decoder.sv | ||
| ibex_controller.sv | ||
| ibex_core.f | ||
| ibex_core.sv | ||
| ibex_core_tracing.sv | ||
| ibex_counter.sv | ||
| ibex_cs_registers.sv | ||
| ibex_csr.sv | ||
| ibex_decoder.sv | ||
| ibex_dummy_instr.sv | ||
| ibex_ex_block.sv | ||
| ibex_fetch_fifo.sv | ||
| ibex_icache.sv | ||
| ibex_id_stage.sv | ||
| ibex_if_stage.sv | ||
| ibex_load_store_unit.sv | ||
| ibex_multdiv_fast.sv | ||
| ibex_multdiv_slow.sv | ||
| ibex_pkg.sv | ||
| ibex_pmp.sv | ||
| ibex_prefetch_buffer.sv | ||
| ibex_register_file_ff.sv | ||
| ibex_register_file_fpga.sv | ||
| ibex_register_file_latch.sv | ||
| ibex_tracer.sv | ||
| ibex_tracer_pkg.sv | ||
| ibex_wb_stage.sv | ||