Tobias Wölfel 0f2dc5c64a [rtl] Avoid latch creation ... Following Verilator warning set default value to avoid the creation of a latch.		2021-01-11 16:20:33 +01:00
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rtl	[rtl] Avoid latch creation	2021-01-11 16:20:33 +01:00
fpga_xilinx.core	Remove lowrisc:prim:clock_gating from shared core collections	2020-07-03 17:08:02 +01:00
sim_shared.core	Remove lowrisc:prim:clock_gating from shared core collections	2020-07-03 17:08:02 +01:00