The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Sven Stucki 85d2632a38 Additional code cleanup and defines		2015-04-07 17:26:40 +02:00
include	Additional code cleanup and defines	2015-04-07 17:26:40 +02:00
alu.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
controller.sv	Fixed indentation in controller (1 level = 2 spaces)	2015-04-07 16:39:28 +02:00
debug_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
ex_stage.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
id_stage.sv	Code cleanup in ID stage	2015-04-07 16:40:45 +02:00
if_stage.sv	Additional code cleanup and defines	2015-04-07 17:26:40 +02:00
instr_core_interface.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
load_store_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
mult.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
register_file.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
riscv_core.sv	Additional code cleanup and defines	2015-04-07 17:26:40 +02:00
wb_stage.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00