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892ad8a621
- Instantiate generic PMP module - Wire up I-side and D-side PMP faults - The output of the PMP check is used to gate external bus requests from the I-side and LSU - Each of those units progresses with their request as-if it was granted externally and registers the PMP error - The error is then sent to the controller at the appropriate time to trigger an exception
70 lines
1.8 KiB
Text
70 lines
1.8 KiB
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:ibex_core:0.1"
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description: "CPU core with 2 stage pipeline implementing the RV32IMC_Zicsr ISA"
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filesets:
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files_rtl:
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files:
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- rtl/ibex_pkg.sv
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- rtl/ibex_alu.sv
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- rtl/ibex_compressed_decoder.sv
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- rtl/ibex_controller.sv
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- rtl/ibex_cs_registers.sv
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- rtl/ibex_decoder.sv
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- rtl/ibex_ex_block.sv
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- rtl/ibex_fetch_fifo.sv
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- rtl/ibex_id_stage.sv
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- rtl/ibex_if_stage.sv
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- rtl/ibex_load_store_unit.sv
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- rtl/ibex_multdiv_fast.sv
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- rtl/ibex_multdiv_slow.sv
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- rtl/ibex_prefetch_buffer.sv
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- rtl/ibex_pmp.sv
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# XXX: Figure out the best way to switch these two implementations
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# dynamically on the target.
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# - rtl/ibex_register_file_latch.sv # ASIC
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- rtl/ibex_register_file_ff.sv # FPGA
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- rtl/ibex_core.sv
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file_type: systemVerilogSource
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files_lint:
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files:
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- dv/uvm/tb/prim_clock_gating.sv: {file_type: systemVerilogSource}
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files_lint_verilator:
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files:
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- lint/verilator_waiver.vlt: {file_type: vlt}
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parameters:
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RVFI:
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datatype: bool
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paramtype: vlogdefine
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SYNTHESIS:
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datatype: bool
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paramtype: vlogdefine
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targets:
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default:
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filesets:
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- files_rtl
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lint:
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filesets:
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# Note on Verilator waivers:
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# You *must* include the waiver file first, otherwise only global waivers
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# are applied, but not file-specific waivers.
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- tool_verilator ? (files_lint_verilator)
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- files_rtl
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- files_lint
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parameters:
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- SYNTHESIS=true
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default_tool: verilator
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toplevel: ibex_core
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tools:
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verilator:
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mode: lint-only
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verilator_options:
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- "-Wall"
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