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https://github.com/openhwgroup/cve2.git
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1002b83ae3
The ibex_pkg.sv file is effectively a "header" with useful defines; we need them in ibex_tracer_pkg.sv, and in other places around Ibex. Currently, the dependency between ibex_tracer_pkg.sv and ibex_pkg.sv wasn't covered in a FuseSoC core file, leading to unstable behavior. This patch adds this dependency by - factoring out the ibex_pkg.sv file into a separate core file, ibex_pkg.core, and - adding a dependency on the new ibex_pkg core to the ibex_tracer core.
138 lines
3.4 KiB
Text
138 lines
3.4 KiB
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:ibex_core:0.1"
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description: "CPU core with 2 stage pipeline implementing the RV32IMC_Zicsr_Zifencei ISA"
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filesets:
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files_rtl:
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depend:
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- lowrisc:prim:assert
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- lowrisc:ibex:ibex_pkg
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files:
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- rtl/ibex_alu.sv
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- rtl/ibex_compressed_decoder.sv
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- rtl/ibex_controller.sv
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- rtl/ibex_cs_registers.sv
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- rtl/ibex_counters.sv
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- rtl/ibex_decoder.sv
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- rtl/ibex_ex_block.sv
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- rtl/ibex_fetch_fifo.sv
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- rtl/ibex_icache.sv
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- rtl/ibex_id_stage.sv
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- rtl/ibex_if_stage.sv
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- rtl/ibex_load_store_unit.sv
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- rtl/ibex_multdiv_fast.sv
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- rtl/ibex_multdiv_slow.sv
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- rtl/ibex_prefetch_buffer.sv
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- rtl/ibex_pmp.sv
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- rtl/ibex_wb_stage.sv
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# XXX: Figure out the best way to switch these two implementations
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# dynamically on the target.
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# - rtl/ibex_register_file_latch.sv # ASIC
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# - rtl/ibex_register_file_fpga.sv # FPGA
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- rtl/ibex_register_file_ff.sv # generic FF-based
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- rtl/ibex_core.sv
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file_type: systemVerilogSource
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files_lint:
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depend:
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- lowrisc:ibex:sim_shared
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files_lint_verilator:
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files:
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- lint/verilator_waiver.vlt: {file_type: vlt}
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files_check_tool_requirements:
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depend:
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- lowrisc:ibex:check_tool_requirements
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parameters:
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RVFI:
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datatype: bool
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paramtype: vlogdefine
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SYNTHESIS:
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datatype: bool
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paramtype: vlogdefine
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RV32E:
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datatype: bool
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paramtype: vlogparam
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RV32M:
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datatype: bool
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paramtype: vlogparam
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MultiplierImplementation:
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datatype: str
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paramtype: vlogparam
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description: "Multiplier implementation. Valid values: fast, slow"
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default: fast
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ICache:
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datatype: bool
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paramtype: vlogparam
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description: "Enable instruction cache"
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default: false
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ICacheECC:
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datatype: bool
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paramtype: vlogparam
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description: "Enable ECC protection in instruction cache"
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default: false
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BranchTargetALU:
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datatype: bool
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paramtype: vlogparam
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default: false
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description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)"
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WritebackStage:
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datatype: bool
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paramtype: vlogparam
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default: false
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description: "Enables third pipeline stage (EXPERIMENTAL)"
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targets:
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default:
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filesets:
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- tool_verilator ? (files_lint_verilator)
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- files_rtl
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- files_check_tool_requirements
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lint:
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filesets:
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- tool_verilator ? (files_lint_verilator)
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- files_rtl
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- files_lint
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- files_check_tool_requirements
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: verilator
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toplevel: ibex_core
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tools:
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verilator:
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mode: lint-only
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verilator_options:
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- "-Wall"
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# RAM primitives wider than 64bit (required for ECC) fail to build in
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# Verilator without increasing the unroll count (see Verilator#1266)
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- "--unroll-count 72"
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veriblelint:
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ruleset: default
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rules:
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- "-parameter-name-style"
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format:
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filesets:
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- files_rtl
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: veribleformat
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toplevel: ibex_core
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tools:
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veribleformat:
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verible_format_args:
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- "--inplace"
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