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This PR makes changes to support Cadence Xcelium 20.09.001 Compile error 1: Fixed the following rtl compile error in ibex_cs_registers.sv assign tselect_rdata = {'b0, tselect_q}; | xmvlog: *E,NONOWD (/proj/riscv_ibex/users/paulok/lowRISC/ibex_1/rtl/ibex_cs_registers.sv,1288|30): Illegal use of a constant without an explicit width specification [4.1.14(IEEE)]. Compile error 2: Fixed the following DV compile error in ibex_mem_intf.sv .data_req_o (data_mem_vif.request ), | xmelab: *E,ICDCBA (./tb/core_ibex_tb_top.sv,89|14): Illegal combination of driver and output clockvar to variable 'request' detected (output clockvar found in clocking block at line 25 in file ./common/ibex_mem_intf_agent/ibex_mem_intf.sv). Simulation probes: Fixed issue with probing in yaml for xrun and added licqueue. Signed-off-by: Paul OKeeffe <paul_okeeffe@crevinn.com> |
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.. | ||
ibex_alu.sv | ||
ibex_branch_predict.sv | ||
ibex_compressed_decoder.sv | ||
ibex_controller.sv | ||
ibex_core.f | ||
ibex_core.sv | ||
ibex_core_tracing.sv | ||
ibex_counter.sv | ||
ibex_cs_registers.sv | ||
ibex_csr.sv | ||
ibex_decoder.sv | ||
ibex_dummy_instr.sv | ||
ibex_ex_block.sv | ||
ibex_fetch_fifo.sv | ||
ibex_icache.sv | ||
ibex_id_stage.sv | ||
ibex_if_stage.sv | ||
ibex_load_store_unit.sv | ||
ibex_multdiv_fast.sv | ||
ibex_multdiv_slow.sv | ||
ibex_pkg.sv | ||
ibex_pmp.sv | ||
ibex_prefetch_buffer.sv | ||
ibex_register_file_ff.sv | ||
ibex_register_file_fpga.sv | ||
ibex_register_file_latch.sv | ||
ibex_tracer.sv | ||
ibex_tracer_pkg.sv | ||
ibex_wb_stage.sv |