97105f42b1
Update code from upstream repository https://github.com/google/riscv- dv to revision e905e9f134e0b7cf7da491218d1a30c75ce8649a * add pass_val and fail_val into csr test flow for EOT correctness checking (Udi) * Support unaligned load/store (Tao Liu) * refactored test generation logic (Udi) * refactored test generation logic (Udi) * Give error when mutually exclusive between -co, and -so argument (dang hai) * documentation, and small fixes (Udi) * no_iss bug (Udi) * no_iss/no_post_compare optional, CSR read_only is now only specified at field level granularity (Udi) * made no_iss optional (Udi) * rm print (Udi) * setup_logging call (Udi) * undo overriding --verbose in run.py, comment cleanup in csr gen script (Udi) * missed verbose arguments (Udi) * verbose arg (Udi) * updated csr description, integrated csr test into flow (Udi) * updated csr description, integrated csr test into flow (Udi) * Enhance verbose information by logging instead of using print (dang hai) * Report date time for output directory (dang hai) * Add main entry point for run.py (dang hai) * Separate command line parser by function (dang hai) * Skip generating S/U mode program for machine mode test (Tao Liu) * minor update to README.md (Tao Liu) * Update the README.md to match command reference from --help (Tao Liu) * Ignore untrack file from python script (dang hai) * Make questa work for new YAML based regression flow (dang hai) * Fix typo in README (Tao Liu) * Fix README google/riscv-dv#54 (Tao Liu) * changed formatting of generator option table (Udi) |
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| .gitignore | ||
| CONTRIBUTING.md | ||
| ibex_core.core | ||
| ibex_core_tracing.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
| README.md | ||
| src_files.yml | ||
Ibex RISC-V Core
Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.
Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include two different choices for the architecture of the multiplier and divider unit, as well as the possibility to drop the support for the "M" extension completely. In addition, the "E" extension can be enabled when opting for a minimum-area configuration.
This core was initially developed as part of the PULP platform under the name "Zero-riscy" [1], and has been contributed to lowRISC who maintains it and develops it further. It is under active development, with further code cleanups, feature additions, and test and verification planned for the future.
Documentation
The Ibex user manual can be
read online at ReadTheDocs. It is also contained in
the doc folder of this repository.
Contributing
We highly appreciate community contributions. To ease our work of reviewing your contributions, please:
- Create your own branch to commit your changes and then open a Pull Request.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages. For more information, please check out the contribution guide.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.
When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.
To get started, please check out the "Good First Issue" list.
Issues and Troubleshooting
If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.
Questions?
Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).