Tom Roberts 6a3200929b [rtl] Add a new top level plus wiring ... This commit creates a new top level wrapping the core, register file and icache RAMs. The tracing top level is also renamed to ibex_top_tracing to match. This new top level is intended to enable a dual core lockstep implementation of Ibex. There are no functional changes in this commit, only wiring. Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>		2021-04-07 12:07:38 +01:00
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verible_waiver.vbw	Add RegFile parameter for selecting register file implementation	2020-08-21 14:20:34 +02:00
verilator_waiver.vlt	[rtl] Add a new top level plus wiring	2021-04-07 12:07:38 +01:00