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ibex_alu.sv
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[rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93)
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2021-12-06 11:14:49 +01:00 |
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ibex_branch_predict.sv
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Fix Xcelium warnings
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2020-11-18 10:16:48 +00:00 |
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ibex_compressed_decoder.sv
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[style] Indent module header with two spaces
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2021-08-31 15:30:28 +02:00 |
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ibex_controller.sv
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[rtl] Move PMP checking to IF stage output
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2021-12-09 18:06:53 +00:00 |
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ibex_core.f
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Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr
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2020-03-06 12:49:51 +01:00 |
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ibex_core.sv
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[rtl] Move PMP checking to IF stage output
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2021-12-09 18:06:53 +00:00 |
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ibex_counter.sv
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[rtl] Fix retired instruction counters
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2021-09-17 12:28:10 +01:00 |
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ibex_cs_registers.sv
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[rtl] Move PMP checking to IF stage output
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2021-12-09 18:06:53 +00:00 |
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ibex_csr.sv
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[style] Indent module header with two spaces
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2021-08-31 15:30:28 +02:00 |
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ibex_decoder.sv
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[rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93)
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2021-12-06 11:14:49 +01:00 |
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ibex_dummy_instr.sv
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[style] Indent module header with two spaces
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2021-08-31 15:30:28 +02:00 |
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ibex_ex_block.sv
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[style] Indent module header with two spaces
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2021-08-31 15:30:28 +02:00 |
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ibex_fetch_fifo.sv
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Move NT branch addr calculation to ID stage
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2021-11-18 13:05:19 +00:00 |
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ibex_icache.sv
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[lint] Fix some AscentLint errors
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2021-12-13 17:52:20 +00:00 |
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ibex_id_stage.sv
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[rtl] Move PMP checking to IF stage output
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2021-12-09 18:06:53 +00:00 |
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ibex_if_stage.sv
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[rtl] Move PMP checking to IF stage output
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2021-12-09 18:06:53 +00:00 |
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ibex_load_store_unit.sv
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[style] Indent module header with two spaces
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2021-08-31 15:30:28 +02:00 |
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ibex_lockstep.sv
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[secded] Switch to inverted ECC codes
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2021-12-02 15:14:11 -08:00 |
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ibex_multdiv_fast.sv
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[style] Indent module header with two spaces
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2021-08-31 15:30:28 +02:00 |
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ibex_multdiv_slow.sv
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[style] Indent module header with two spaces
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2021-08-31 15:30:28 +02:00 |
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ibex_pkg.sv
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[rtl] Move PMP checking to IF stage output
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2021-12-09 18:06:53 +00:00 |
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ibex_pmp.sv
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[style] Indent module header with two spaces
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2021-08-31 15:30:28 +02:00 |
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ibex_prefetch_buffer.sv
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[rtl] Move PMP checking to IF stage output
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2021-12-09 18:06:53 +00:00 |
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ibex_register_file_ff.sv
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[secded] Switch to inverted ECC codes
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2021-12-02 15:14:11 -08:00 |
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ibex_register_file_fpga.sv
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[rtl] Replace always_ff with always @(posedge .. in FPGA regfile
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2021-12-09 16:35:31 +01:00 |
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ibex_register_file_latch.sv
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[secded] Switch to inverted ECC codes
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2021-12-02 15:14:11 -08:00 |
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ibex_top.sv
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[ibex_top] Use correct ECC codeword for '0 reset in regfile
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2021-12-08 08:54:54 +00:00 |
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ibex_top_tracing.sv
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[rtl] RVFI changes and extensions for co-simulation
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2021-10-15 11:30:35 +01:00 |
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ibex_tracer.sv
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[rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93)
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2021-12-06 11:14:49 +01:00 |
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ibex_tracer_pkg.sv
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[rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93)
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2021-12-06 11:14:49 +01:00 |
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ibex_wb_stage.sv
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[rtl] Fix retired instruction counters
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2021-09-17 12:28:10 +01:00 |
