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Update code from upstream repository https://github.com/google/riscv- dv to revision 2e5251846efb5fa42882a2b6b571ef8693e8cd60 * Remove f strings for Python 3.5-compatibility (Philipp Wagner) * Fix start-end pair mismatch in asm file (aneels3) * Fix AMO instruction constraint issue (google/riscv-dv#682) (taoliug) * - Adds support for the coverage report visualization (pyucis-viewer) - Adds CSR, opcode, rv32i_misc, and mepc_alignment covergroups (Hodjat Asghari Esfeden) * fix Todo of directed_lib (aneels3) * Added avail_regs_c constraint (ShraddhaDevaiya) * Fix factory method implementation (aneels3) * Add directed instr (aneels3) * fix label issue (aneels3) * fix randomization issue (aneels3) * Fix typo (aneels3) * add riscv_pseudo_instr (aneels3) * add value_plusargs functionality (pvipsyash) * add riscv_utils and fix minor issues (aneels3) * modify for directed scenario (pvipsyash) * Fix a minor issue with the instruction PC (Hodjat Asghari Esfeden) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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eembc_coremark | ||
google_riscv-dv | ||
lowrisc_ip | ||
patches | ||
eembc_coremark.lock.hjson | ||
google_riscv-dv.lock.hjson | ||
google_riscv-dv.vendor.hjson | ||
lowrisc_ip.lock.hjson | ||
lowrisc_ip.vendor.hjson |