udinator 4a1806f16f Update google_riscv-dv to google/riscv-dv@ad6fe56 (#385) ... Update code from upstream repository https://github.com/google/riscv- dv to revision ad6fe565a91445cc3ea3e32119360b57af4f19b2 * Workaround for dsim compile issue (google/riscv-dv#211) (taoliug) * Add a --seed_yaml option to rerun a regression with the same seed of a prior regression (google/riscv-dv#210) (taoliug) * Update questa covearge options (google/riscv-dv#209) (taoliug) * Fix disable_compressed_instr option (google/riscv-dv#205) (taoliug) * Fix non-compressed instruction test (google/riscv-dv#203) (taoliug) * Debug single step functionality and config knobs (Udi) * Fix no_branch_jump option (google/riscv-dv#200) (taoliug) * Add more functional covergroup (google/riscv-dv#199) (taoliug) * Allow randomly reserve GPR for TP/SP, improve functional coverage (google/riscv-dv#198) (taoliug) * Allow running the coverage script with LSF (google/riscv-dv#195) (taoliug) * Add support for disable_compressed_instr (google/riscv-dv#194) (taoliug) * Improve coverage collection performance (google/riscv-dv#193) (taoliug) * Signature_addr_reg constraint update (Udi) * Add a debug mode for functional coverage (google/riscv-dv#191) (taoliug) * Fix typo in README (google/riscv-dv#189) (taoliug) * Constrain scratch_reg (google/riscv-dv#188) (udinator) * Update README for the coverage flow (google/riscv-dv#187) (taoliug) * Add basic privileged CSR cover group (google/riscv-dv#186) (taoliug) * Fix cover point definition (google/riscv-dv#185) (taoliug) * Fix ovpsim log compare issue (google/riscv-dv#183) (udinator)		2019-10-08 14:22:05 -07:00
..
google_riscv-dv	Update google_riscv-dv to google/riscv-dv@ad6fe56 (#385)	2019-10-08 14:22:05 -07:00
google_riscv-dv.lock.hjson	Update google_riscv-dv to google/riscv-dv@ad6fe56 (#385)	2019-10-08 14:22:05 -07:00
google_riscv-dv.vendor.hjson	Integrate riscv-dv upstream changes (#107)	2019-07-01 08:59:31 -07:00