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0778008f33
This commit replaces all X assignments in the RTL with defined values. In addition, SystemVerilog Assertions are added to catch invalid signal values in simulation. A new file containing the corresponding assertion macros is added as well. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
19 lines
477 B
Text
19 lines
477 B
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:ibex_tracer:0.1"
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description: "Tracer for use with Ibex using the RVFI interface"
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filesets:
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files_rtl:
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depend:
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- lowrisc:prim:assert
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files:
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- rtl/ibex_tracer_pkg.sv
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- rtl/ibex_tracer.sv
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file_type: systemVerilogSource
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targets:
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default:
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filesets:
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- files_rtl
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