cve2/rtl
Rupert Swarbrick c15f3b8888 [icache] Define some fake DPI functions to simplify linking
This is triggered by the fact that if the ICache parameter is false
then we don't instantiate the ibex_icache module. For verilator
simulations, the module is then discarded entirely, which means that
its two DPI functions are not defined. That's unfortunate because
we're also compiling the code in scrambled_ecc32_mem_area.cc, which
expects the functions to be defined.

The obvious solution (don't include scrambled_ecc32_mem_area.cc if you
don't have an icache) isn't easy to do, because FuseSoc doesn't
currently allow us to use parameters to configure its dependency
tree (see fusesoc issue 438 for a discussion).

The super-clever solution that I came up with before(!) was to declare
these symbols as weak in the C++ code. That way, we can do a runtime
check to make sure that no-one is silly enough to call them without an
icache, but everything will still build properly either way.

Unfortunately, that doesn't work well with xcelium simulations.
Xcelium turns out to compile all the C++ code into one .so library and
generate functions for exported DPI functions in another. These two
solibs then get loaded at runtime with dlopen(). But this doesn't work
with weak symbols: in fact, it seems you end up with the C++ version
every time. Boo!

So let's be stupider about it and define (bogus) versions of the DPI
functions in this case. Fortunately, both of them are designed to
return zero on failure so we can just return zero and needn't worry
too much.

The idea is that when this lands, we can revert the OpenTitan change
that switched the C++ code to using weak symbols and Xcelium
simulations will start working.
2022-03-03 13:48:10 +00:00
..
ibex_alu.sv [bitmanip] Add new configuration option for OpenTitan Earl Grey 2021-12-16 14:18:00 +01:00
ibex_branch_predict.sv Fix Xcelium warnings 2020-11-18 10:16:48 +00:00
ibex_compressed_decoder.sv [style] Indent module header with two spaces 2021-08-31 15:30:28 +02:00
ibex_controller.sv [rtl] Move PMP checking to IF stage output 2021-12-09 18:06:53 +00:00
ibex_core.f Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr 2020-03-06 12:49:51 +01:00
ibex_core.sv [rtl] Switch to multi-bit fetch enable 2022-02-21 15:35:35 +00:00
ibex_counter.sv [rtl] Fix retired instruction counters 2021-09-17 12:28:10 +01:00
ibex_cs_registers.sv [rtl] Fix AscentLint errors 2022-02-17 07:51:58 +01:00
ibex_csr.sv [style] Indent module header with two spaces 2021-08-31 15:30:28 +02:00
ibex_decoder.sv [rtl] Remove redundant comments in decoder 2021-12-16 14:18:00 +01:00
ibex_dummy_instr.sv [style] Indent module header with two spaces 2021-08-31 15:30:28 +02:00
ibex_ex_block.sv [style] Indent module header with two spaces 2021-08-31 15:30:28 +02:00
ibex_fetch_fifo.sv Move NT branch addr calculation to ID stage 2021-11-18 13:05:19 +00:00
ibex_icache.sv [icache] Add RAM Primitives for scrambling 2022-01-19 14:59:43 +00:00
ibex_id_stage.sv [rtl] Move PMP checking to IF stage output 2021-12-09 18:06:53 +00:00
ibex_if_stage.sv [icache] Define some fake DPI functions to simplify linking 2022-03-03 13:48:10 +00:00
ibex_load_store_unit.sv [style] Indent module header with two spaces 2021-08-31 15:30:28 +02:00
ibex_lockstep.sv [rtl] Switch to multi-bit fetch enable 2022-02-21 15:35:35 +00:00
ibex_multdiv_fast.sv [style] Indent module header with two spaces 2021-08-31 15:30:28 +02:00
ibex_multdiv_slow.sv [style] Indent module header with two spaces 2021-08-31 15:30:28 +02:00
ibex_pkg.sv [rtl] Switch to multi-bit fetch enable 2022-02-21 15:35:35 +00:00
ibex_pmp.sv [style] Indent module header with two spaces 2021-08-31 15:30:28 +02:00
ibex_pmp_reset_default.svh [rtl,doc] Add customisable PMP reset values 2022-01-24 10:01:36 +00:00
ibex_prefetch_buffer.sv [rtl] Move PMP checking to IF stage output 2021-12-09 18:06:53 +00:00
ibex_register_file_ff.sv [secded] Switch to inverted ECC codes 2021-12-02 15:14:11 -08:00
ibex_register_file_fpga.sv [rtl] Replace always_ff with always @(posedge .. in FPGA regfile 2021-12-09 16:35:31 +01:00
ibex_register_file_latch.sv [secded] Switch to inverted ECC codes 2021-12-02 15:14:11 -08:00
ibex_top.sv [dv] Add X assertions for top-level IO 2022-02-24 14:53:21 +00:00
ibex_top_tracing.sv [rtl] Switch to multi-bit fetch enable 2022-02-21 15:35:35 +00:00
ibex_tracer.sv [ibex_tracer] Void cast function calls 2022-01-20 16:59:22 -08:00
ibex_tracer_pkg.sv [rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93) 2021-12-06 11:14:49 +01:00
ibex_wb_stage.sv [rtl] Fix retired instruction counters 2021-09-17 12:28:10 +01:00