docs /datasheet
Update documentation and instruction tracer for new encoding
2016-01-21 14:30:11 +01:00
include
Fix issues in instruction tracer and align with virtual platform
2016-02-04 16:43:27 +01:00
.gitignore
Added vim swap file
2015-07-24 15:26:32 +02:00
alu.sv
Clean headers
2015-12-14 16:39:16 +01:00
compressed_decoder.sv
Clean headers
2015-12-14 16:39:16 +01:00
controller.sv
Change to new encoding from Eric
2016-01-21 13:08:16 +01:00
cs_registers.sv
Remove mscratch and change the way csr works
2015-12-26 00:15:00 +01:00
debug_unit.sv
Clean headers
2015-12-14 16:39:16 +01:00
decoder.sv
Change to new encoding from Eric
2016-01-21 13:08:16 +01:00
ex_stage.sv
Remove mscratch and change the way csr works
2015-12-26 00:15:00 +01:00
exc_controller.sv
Clean headers
2015-12-14 16:39:16 +01:00
hwloop_controller.sv
Clean headers
2015-12-14 16:39:16 +01:00
hwloop_regs.sv
Clean headers
2015-12-14 16:39:16 +01:00
id_stage.sv
Fix net declaration
2016-01-21 15:11:32 +01:00
if_stage.sv
only jump once even when there are stalls
2015-12-26 13:30:44 +01:00
LICENSE
Added LICENSE file and started adding headers
2015-12-11 17:20:07 +01:00
load_store_unit.sv
Clean headers
2015-12-14 16:39:16 +01:00
mult.sv
Clean headers
2015-12-14 16:39:16 +01:00
prefetch_buffer.sv
Make sure the address is kept stable when we are waiting for a gnt
2016-01-23 00:35:01 +01:00
prefetch_L0_buffer.sv
Clean headers
2015-12-14 16:39:16 +01:00
register_file.sv
Clean headers
2015-12-14 16:39:16 +01:00
register_file_ff.sv
Clean headers
2015-12-14 16:39:16 +01:00
riscv_core.sv
Move to classes for tracer
2016-02-02 17:31:26 +01:00
riscv_tracer.sv
Fix issues in instruction tracer and align with virtual platform
2016-02-04 16:43:27 +01:00
src_files.txt
added FPGA-friendly register file to src_files.txt
2016-02-11 16:07:09 +01:00