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The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
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Add riscv-dv vendor configuration and patches as basis for including the RISC-V DV code in a follow-up commit.
2019-05-31 08:58:21 +01:00
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README.md

Ibex: RISC-V Core

Ibex is a small 32 bit RISC-V core with a 2-stage pipeline.

Ibex fully implements the RV32IMC instruction set and a small set of RISC-V privileged specifications. Ibex can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensions.

This core was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further.

Ibex is under active development, with further code cleanups, feature additions, and test and verification planned for the future.

Documentation

The Ibex documentation can be read online at ReadTheDocs. It is also contained in the doc folder of this repository. We highly appreciate pull requests on the documentation if you find anything wrong or outdated!

License

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).