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cve2/shared/rtl/fpga/xilinx
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Tobias Wölfel 76f6a3d4c3 Use shared code for Arty A7-100T example 
Move Xilinx specific code into shared folder so it can be re-used by
different examples.
Use the shared RAM code and make use of byte enable signal.
Fixes lowrisc/ibex#144
2019-11-14 13:20:19 +01:00
..
clkgen_xil7series.sv Use shared code for Arty A7-100T example 2019-11-14 13:20:19 +01:00
prim_clock_gating.sv Use shared code for Arty A7-100T example 2019-11-14 13:20:19 +01:00