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This commit implements the Bit Manipulation Extension ZBB instruction
group: clz, ctz, pcnt, slo, sro, rol, ror, rev, rev8, orcb, pack
packu, packh, min, max, andn, orn, and xnor.
* Bit counting instructions clz, ctz and pcnt can be implemented to
share much of the architecture:
clz: Count Leading Zeros. Counts the number of 0 bits at the
MSB end of the argument.
ctz: Count Trailing Zeros. Counts the number of 0 bits at the
LSB end of the argument.
pcnt: Counts the number of set bits of the argument.
The implementation uses:
- 32 one bit adders, counting the set bits of a signal
bitcnt_bits, starting from the LSB end.
- For pcnt the argument is fed directly into bitcnt_bits.
- For clz, the operand is reversed such that leading zeros are
located at the LSB end of bitcnt_bits.
- For ctz and clz: counter enable signal for 1-bit counter i
is high, if the previous enable signal, and
its corresponting bitcnt_bit was high.
* Instructions sll[i], srl[i],slo[i], sro[i], rol, ror[i], rev, rev8
and orc.b are summarized as shifting instructions and related:
The following instructions are slight variations of the
existing base spec's sll, srl and sra instructions.
- slo[i] and sro[i]: shift left/right ones: similar to
shift-logical operations from base spec, but shifting
in ones instead of zeros.
- rol and ror[i]: rotate left/right ones: circular shift
operations. shifting in values from the oposite end
of the operand instead of zeros.
Those instructions can be implemented, sharing the base spec's
shifting structure. In order to support rotate operations, a
64-bit shifting structure is needed.
In the existing ALU, hardware is described only for right
shifts. For left shifts the operand is initially reversed,
right shifted and the result is reversed back. This gives rise
to an additional resource sharing oportunity for some more
zbb operations:
- rev: bitwise reversal.
- rev8: byte-order swap.
- orc.b: byte-wise reverse and or-combine.
* Instructions min, max:
For the B-extension's min/max instructions, we can share the
existing comparison operations. The result is obtained by
activating the comparison structure accordingly and
multiplexing the operands using the comparison result.
* Logic-with-negate instructions andn, orn, xnor:
For the B-extension's logic-with-negate instructions we can
share the structures of the base spec's logic structures
already present for 'xnor', 'or' and 'and' instructions as
well as the conditionally negated b operand generated for
subtraction operations.
* Instructions pack, packu, packh:
For the pack, packh and packu instructions I don't see any
opportunities for resource sharing. However, the architecture
is quite simple.
- pack: pack the lower halves of rs1 and rs2 into rd, with rs1
in the lower half and rs2 in the upper half.
- packu: pack the upper halves of rs1 and rs2 into rd, with
rs1 in the lower half and rs2 in the upper half.
- packh: pack the LSB bytes of rs1 and rs2 into rd, with rs1
in the lower half and rs2 in the upper half.
Signed-off-by: ganoam <gnoam@live.com>
130 lines
6.7 KiB
ReStructuredText
130 lines
6.7 KiB
ReStructuredText
.. _instruction-decode-execute:
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Instruction Decode and Execute
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==============================
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.. figure:: images/de_ex_stage.svg
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:name: de_ex_stage
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:align: center
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Instruction Decode and Execute
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The Instruction Decode and Execute stage takes instruction data from the instruction fetch stage (which has been converted to the uncompressed representation in the compressed instruction case).
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The instructions are decoded and executed all within one cycle including the register read and write.
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The stage is made up of multiple sub-blocks which are described below.
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Instruction Decode Block (ID)
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-----------------------------
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Source File: :file:`rtl/ibex_id_stage.sv`
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The Instruction Decode (ID) controls the overall decode/execution process.
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It contains the muxes to choose what is sent to the ALU inputs and where the write data for the register file comes from.
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A small state machine is used to control multi-cycle instructions (see :ref:`pipeline-details` for more details), which stalls the whole stage whilst a multi-cycle instruction is executing.
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Controller
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----------
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Source File: :file:`rtl/ibex_controller.sv`
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The Controller contains the state machine that controls the overall execution of the processor.
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It is responsible for:
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* Handling core startup from reset
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* Setting the PC for the IF stage on jump/branch
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* Dealing with exceptions/interrupts (jump to appropriate PC, set relevant CSR values)
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* Controlling sleep/wakeup on WFI
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* Debugging control
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Decoder
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-------
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Source File: :file:`rtl/ibex_decoder.sv`
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The decoder takes uncompressed instruction data and issues appropriate control signals to the other blocks to execute the instruction.
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Register File
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-------------
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Source Files: :file:`rtl/ibex_register_file_ff.sv` :file:`rtl/ibex_register_file_latch.sv`
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See :ref:`register-file` for more details.
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Execute Block
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-------------
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Source File: :file:`rtl/ibex_ex_block.sv`
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The execute block contains the ALU and the multiplier/divider blocks, it does little beyond wiring and instantiating these blocks.
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Arithmetic Logic Unit (ALU)
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---------------------------
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Source File: :file:`rtl/ibex_alu.sv`
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The Arithmetic Logic Logic (ALU) is a purely combinational block that implements operations required for the Integer Computational Instructions and the comparison operations required for the Control Transfer Instructions in the RV32I RISC-V Specification.
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Other blocks use the ALU for the following tasks:
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* Mult/Div uses it to perform addition as part of the multiplication and division algorithms
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* It computes branch targets with a PC + Imm calculation
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* It computes memory addresses for loads and stores with a Reg + Imm calculation
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* The LSU uses it to increment addresses when performing two accesses to handle an unaligned access
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Support for the RISC-V Bitmanipulation Extension is enabled via the parameter ``RV32B``.
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This feature is *EXPERIMENTAL* and the details of its impact are not yet documented here.
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Currently only the Zbb base extension is implemented.
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All instructions are carried out in a single clock cycle.
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.. _mult-div:
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Multiplier/Divider Block (MULT/DIV)
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-----------------------------------
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Source Files: :file:`rtl/ibex_multdiv_slow.sv` :file:`rtl/ibex_multdiv_fast.sv`
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The Multiplier/Divider (MULT/DIV) is a state machine driven block to perform multiplication and division.
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The fast and slow versions differ in multiplier only. All versions implement the same form of long division algorithm. The ALU block is used by the long division algorithm in all versions.
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Multiplier
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The multiplier can be implemented in three variants controlled via the parameter ``MultiplierImplementation``.
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Single-Cycle Multiplier
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This implementation is chosen by setting the ``MultiplierImplementation`` parameter to "single-cycle". The single-cycle multiplier makes use of three parallel multiplier units, designed to be mapped to hardware multiplier primitives on FPGAs. It is therefore the **first choice for FPGA synthesis**.
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- Using three parallel 17-bit x 17-bit multiplication units and a 34-bit accumulator, it completes a MUL instruction in 1 cycle. MULH is completed in 2 cycles.
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- This MAC is internal to the mult/div block (no external ALU use).
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- Beware it is simply implemented with the ``*`` and ``+`` operators so results heavily depend upon the synthesis tool used.
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- ASIC synthesis has not yet been tested but is expected to consume 3-4x the area of the fast multiplier for ASIC.
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Fast Multi-Cycle Multiplier
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This implementation is chosen by setting the ``MultiplierImplementation`` parameter to "fast". The fast multi-cycle multiplier provides a reasonable trade-off between area and performance. It is the **first choice for ASIC synthesis**.
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- Completes multiply in 3-4 cycles using a MAC (multiply accumulate) which is capable of a 17-bit x 17-bit multiplication with a 34-bit accumulator.
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- A MUL instruction takes 3 cycles, MULH takes 4.
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- This MAC is internal to the mult/div block (no external ALU use).
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- Beware it is simply implemented with the ``*`` and ``+`` operators so results heavily depend upon the synthesis tool used.
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- In some cases it may be desirable to replace this with a specific implementation such as an explicit gate level implementation.
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Slow Multi-Cycle Multiplier
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To select the slow multi-cycle multiplier, set the ``MultiplierImplementation`` parameter to "slow".
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- Completes multiply in clog2(``op_b``) + 1 cycles (for MUL) or 33 cycles (for MULH) using a Baugh-Wooley multiplier.
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- The ALU block is used to compute additions.
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Divider
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Both the fast and slow blocks use the same long division algorithm, it takes 37 cycles to compute (though only requires 2 cycles when there is a divide by 0) and proceeds as follows:
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- Cycle 0: Check for divide by 0
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- Cycle 1: Compute absolute value of operand A (or return result on divide by 0)
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- Cycle 2: Compute absolute value of operand B
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- Cycles 4 - 36: Perform long division as described here: https://en.wikipedia.org/wiki/Division_algorithm#Integer_division_(unsigned)_with_remainder.
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Control and Status Register Block (CSR)
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---------------------------------------
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Source File: :file:`rtl/ibex_cs_registers.sv`
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The CSR contains all of the CSRs (control/status registers).
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Any CSR read/write is handled through this block.
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Performance counters are held in this block and incremented when appropriate (this includes ``mcycle`` and ``minstret``).
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Read data from a CSR is available the same cycle it is requested.
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Further detail on the implemented CSRs can be found in :ref:`cs-registers`
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Load-Store Unit (LSU)
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---------------------
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Source File: :file:`rtl/ibex_load_store_unit.sv`
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The Load-Store Unit (LSU) interfaces with main memory to perform load and store operations.
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See :ref:`load-store-unit` for more details.
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