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ba9b137488
Fusesoc has an unfortunate bug[1] where a boolean parameter which has default true can't be disabled. For now, just make all our boolean parameters back into integers again. In the future, when that's fixed, maybe we should switch things back. [1] https://github.com/olofk/fusesoc/issues/392
136 lines
3.1 KiB
Text
136 lines
3.1 KiB
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:ibex_core_tracing:0.1"
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description: "Ibex CPU core with tracing enabled"
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filesets:
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files_rtl:
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depend:
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- lowrisc:ibex:ibex_core
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- lowrisc:ibex:ibex_tracer
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files:
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- rtl/ibex_core_tracing.sv
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file_type: systemVerilogSource
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files_lint:
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depend:
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- lowrisc:ibex:sim_shared
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files_lint_verilator:
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files:
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- lint/verilator_waiver.vlt: {file_type: vlt}
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parameters:
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# The tracer uses the RISC-V Formal Interface (RVFI) to collect trace signals.
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RVFI:
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datatype: bool
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paramtype: vlogdefine
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default: true
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SYNTHESIS:
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datatype: bool
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paramtype: vlogdefine
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RV32E:
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datatype: int
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default: 0
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paramtype: vlogparam
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RV32M:
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datatype: int
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default: 1
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paramtype: vlogparam
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RV32B:
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datatype: int
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default: 0
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paramtype: vlogparam
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MultiplierImplementation:
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datatype: str
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paramtype: vlogparam
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description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
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default: "fast"
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ICache:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable instruction cache"
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ICacheECC:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable ECC protection in instruction cache"
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BranchTargetALU:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
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WritebackStage:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
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SecureIbex:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
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targets:
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default:
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filesets:
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- files_rtl
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parameters:
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- RVFI=true
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lint:
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filesets:
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# Note on Verilator waivers:
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# You *must* include the waiver file first, otherwise only global waivers
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# are applied, but not file-specific waivers.
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- tool_verilator ? (files_lint_verilator)
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- files_rtl
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- files_lint
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parameters:
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- RVFI=true
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- SYNTHESIS=true
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- RV32M
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- RV32E
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- RV32B
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- BranchTargetALU
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- WritebackStage
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- MultiplierImplementation
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- SecureIbex
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default_tool: verilator
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toplevel: ibex_core_tracing
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tools:
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verilator:
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mode: lint-only
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verilator_options:
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- "-Wall"
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# RAM primitives wider than 64bit (required for ECC) fail to build in
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# Verilator without increasing the unroll count (see Verilator#1266)
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- "--unroll-count 72"
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veriblelint:
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ruleset: default
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rules:
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- "-parameter-name-style"
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format:
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filesets:
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- files_rtl
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: veribleformat
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toplevel: ibex_core
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tools:
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veribleformat:
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verible_format_args:
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- "--inplace"
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