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066ff47261
* remove parameter BranchPredictor Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove references to the removed parameter(s) from examples Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from compliance verification Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from core lists Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from the example configurations Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove references to the removed parameter from documentation Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove related and dead code Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> --------- Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
114 lines
2.9 KiB
Text
114 lines
2.9 KiB
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "openhwgroup:cve2:cve2_top:0.1"
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description: "Ibex, a small RV32 CPU core"
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filesets:
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files_rtl:
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depend:
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- openhwgroup:cve2:cve2_pkg
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- openhwgroup:cve2:cve2_core
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- lowrisc:prim:buf
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- lowrisc:prim:clock_mux2
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- lowrisc:prim:flop
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- lowrisc:prim:ram_1p_scr
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files:
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- rtl/cve2_register_file_ff.sv # generic FF-based
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- rtl/cve2_top.sv
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file_type: systemVerilogSource
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files_lint_verilator:
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files:
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- lint/verilator_waiver.vlt: {file_type: vlt}
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files_lint_verible:
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files:
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- lint/verible_waiver.vbw: {file_type: veribleLintWaiver}
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files_check_tool_requirements:
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depend:
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- lowrisc:tool:check_tool_requirements
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files_clk_gate:
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files:
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- bhv/cve2_sim_clock_gate.sv
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file_type: systemVerilogSource
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parameters:
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RVFI:
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datatype: bool
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paramtype: vlogdefine
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SYNTHESIS:
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datatype: bool
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paramtype: vlogdefine
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FPGA_XILINX:
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datatype: bool
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description: Identifies Xilinx FPGA targets to set DSP pragmas for performance counters.
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default: false
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paramtype: vlogdefine
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RV32E:
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datatype: int
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default: 0
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paramtype: vlogparam
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RV32M:
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datatype: str
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default: cve2_pkg::RV32MFast
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paramtype: vlogdefine
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description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values."
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RV32B:
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datatype: str
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default: cve2_pkg::RV32BNone
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paramtype: vlogdefine
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description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
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targets:
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default: &default_target
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filesets:
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- tool_verilator ? (files_lint_verilator)
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- tool_veriblelint ? (files_lint_verible)
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- files_rtl
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- target_sim ? (files_clk_gate)
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toplevel: cve2_top
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parameters:
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- tool_vivado ? (FPGA_XILINX=true)
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lint:
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<<: *default_target
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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filesets_append:
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- files_clk_gate
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default_tool: verilator
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tools:
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verilator:
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mode: lint-only
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verilator_options:
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- "-Wall"
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# RAM primitives wider than 64bit (required for ECC) fail to build in
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# Verilator without increasing the unroll count (see Verilator#1266)
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- "--unroll-count 72"
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format:
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filesets:
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- files_rtl
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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default_tool: veribleformat
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toplevel: cve2_top
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tools:
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veribleformat:
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verible_format_args:
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- "--inplace"
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- "--formal_parameters_indentation=indent"
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- "--named_parameter_indentation=indent"
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- "--named_port_indentation=indent"
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- "--port_declarations_indentation=indent"
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