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111 lines
5.1 KiB
ReStructuredText
111 lines
5.1 KiB
ReStructuredText
.. _instruction-decode-execute:
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Instruction Decode and Execute
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==============================
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.. figure:: images/de_ex_stage.svg
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:name: de_ex_stage
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:align: center
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Instruction Decode and Execute
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The Instruction Decode and Execute stage takes instruction data from the instruction fetch stage (which has been converted to the uncompressed representation in the compressed instruction case).
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The instructions are decoded and executed all within one cycle including the register read and write.
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The stage is made up of multiple sub-blocks which are described below.
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Instruction Decode Block (ID)
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-----------------------------
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Source File: :file:`rtl/ibex_id_stage.sv`
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The Instruction Decode (ID) controls the overall decode/execution process.
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It contains the muxes to choose what is sent to the ALU inputs and where the write data for the register file comes from.
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A small state machine is used to control multi-cycle instructions (see :ref:`pipeline-details` for more details), which stalls the whole stage whilst a multi-cycle instruction is executing.
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Controller
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----------
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Source File: :file:`rtl/ibex_controller.sv`
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The Controller contains the state machine that controls the overall execution of the processor.
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It is responsible for:
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* Handling core startup from reset
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* Setting the PC for the IF stage on jump/branch
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* Dealing with exceptions/interrupts (jump to appropriate PC, set relevant CSR values)
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* Controlling sleep/wakeup on WFI
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* Debugging control
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Decoder
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-------
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Source File: :file:`rtl/ibex_decoder.sv`
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The decoder takes uncompressed instruction data and issues appropriate control signals to the other blocks to execute the instruction.
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Register File
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-------------
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Source Files: :file:`rtl/ibex_register_file_ff.sv` :file:`rtl/ibex_register_file_latch.sv`
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See :ref:`register-file` for more details.
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Execute Block
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-------------
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Source File: :file:`rtl/ibex_ex_block.sv`
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The execute block contains the ALU and the multiplier/divider blocks, it does little beyond wiring and instantiating these blocks.
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Arithmetic Logic Unit (ALU)
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---------------------------
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Source File: :file:`rtl/ibex_alu.sv`
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The Arithmetic Logic Logic (ALU) is a purely combinational block that implements operations required for the Integer Computational Instructions and the comparison operations required for the Control Transfer Instructions in the RV32I RISC-V Specification.
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Other blocks use the ALU for the following tasks:
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* Mult/Div uses it to perform addition as part of the multiplication and division algorithms
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* It computes branch targets with a PC + Imm calculation
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* It computes memory addresses for loads and stores with a Reg + Imm calculation
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* The LSU uses it to increment addresses when performing two accesses to handle an unaligned access
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.. _mult-div:
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Multiplier/Divider Block (MULT/DIV)
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-----------------------------------
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Source Files: :file:`rtl/ibex_multdiv_slow.sv` :file:`rtl/ibex_multdiv_fast.sv`
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The Multiplier/Divider (MULT/DIV) is a state machine driven block to perform multiplication and division.
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The fast and slow versions differ in multiplier only, both implement the same form of long division algorithm.
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The ALU block is used by the long division algorithm in both the fast and slow blocks.
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Fast Multiplier
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- Completes multiply in 3-4 cycles using a MAC (multiply accumulate) which is capable of a 17-bit x 17-bit multiplication with a 34-bit accumulator.
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- A MUL instruction takes 3 cycles, MULH takes 4.
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- This MAC is internal to the mult/div block (no external ALU use).
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- Beware it is simply implemented with the ``*`` and ``+`` operators so results heavily depend upon the synthesis tool used.
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- In some cases it may be desirable to replace this with a specific implementation (such as a hard macro in an FPGA or an explicit gate level implementation).
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Slow Multiplier
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- Completes multiply in 33 cycles using a Baugh-Wooley multiplier (for both MUL and MULH).
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- The ALU block is used to compute additions.
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Divider
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Both the fast and slow blocks use the same long division algorithm, it takes 37 cycles to compute (though only requires 2 cycles when there is a divide by 0) and proceeds as follows:
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- Cycle 0: Check for divide by 0
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- Cycle 1: Compute absolute value of operand A (or return result on divide by 0)
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- Cycle 2: Compute absolute value of operand B
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- Cycles 4 - 36: Perform long division as described here: https://en.wikipedia.org/wiki/Division_algorithm#Integer_division_(unsigned)_with_remainder.
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Control and Status Register Block (CSR)
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---------------------------------------
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Source File: :file:`rtl/ibex_cs_registers.sv`
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The CSR contains all of the CSRs (control/status registers).
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Any CSR read/write is handled through this block.
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Performance counters are held in this block and incremented when appropriate (this includes ``mcycle`` and ``minstret``).
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Read data from a CSR is available the same cycle it is requested.
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Further detail on the implemented CSRs can be found in :ref:`cs-registers`
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Load-Store Unit (LSU)
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---------------------
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Source File: :file:`rtl/ibex_load_store_unit.sv`
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The Load-Store Unit (LSU) interfaces with main memory to perform load and store operations.
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See :ref:`load-store-unit` for more details.
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