mirror of
https://github.com/openhwgroup/cve2.git
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60 lines
893 B
YAML
60 lines
893 B
YAML
riscv:
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incdirs: [
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include,
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]
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files: [
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include/riscv_defines.sv,
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include/riscv_tracer_defines.sv,
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alu.sv,
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alu_simplified.sv,
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alu_div.sv,
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compressed_decoder.sv,
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controller.sv,
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cs_registers.sv,
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debug_unit.sv,
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decoder.sv,
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exc_controller.sv,
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ex_stage.sv,
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hwloop_controller.sv,
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hwloop_regs.sv,
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id_stage.sv,
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if_stage.sv,
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load_store_unit.sv,
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mult.sv,
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prefetch_buffer.sv,
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prefetch_buffer_small.sv,
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prefetch_L0_buffer.sv,
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riscv_core.sv,
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]
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riscv_vip_rtl:
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targets: [
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rtl,
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]
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incdirs: [
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include,
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]
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files: [
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riscv_tracer.sv,
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riscv_simchecker.sv,
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]
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riscv_regfile_rtl:
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targets: [
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rtl,
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]
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incdirs: [
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include,
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]
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files: [
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register_file.sv,
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]
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riscv_regfile_fpga:
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targets: [
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xilinx,
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]
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incdirs: [
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include,
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]
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files: [
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register_file_ff.sv,
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]
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