mirror of
https://github.com/xarc/harv.git
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Changes in signals names
This commit is contained in:
Douglas Santos
parent
24c0e08825
commit
2d54e7cbc2
4 changed files with 307 additions and 308 deletions
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@ -9,12 +9,12 @@ entity control is
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port (
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-- input ports
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-- processor status
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imem_gnt_i : in std_logic;
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imem_err_i : in std_logic;
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dmem_gnt_i : in std_logic;
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dmem_outofrange_i : in std_logic;
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dmem_sbu_i : in std_logic;
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dmem_dbu_i : in std_logic;
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imem_gnt_i : in std_logic;
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imem_err_i : in std_logic;
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dmem_gnt_i : in std_logic;
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dmem_err_i : in std_logic;
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dmem_sbu_i : in std_logic;
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dmem_dbu_i : in std_logic;
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-- instruction decode
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opcode_i : in std_logic_vector(6 downto 0);
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@ -29,8 +29,8 @@ entity control is
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-- output ports
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-- processor status
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imem_req_o : out std_logic;
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dmem_req_o : out std_logic;
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imem_req_o : out std_logic;
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dmem_req_o : out std_logic;
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update_pc_o : out std_logic;
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trap_o : out std_logic;
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@ -42,7 +42,7 @@ entity control is
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imm_shamt_o : out std_logic;
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imm_up_o : out std_logic;
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-- register bank
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regwr_o : out std_logic;
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regwr_o : out std_logic;
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-- control transfer
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inv_branch_o : out std_logic;
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branch_o : out std_logic;
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@ -50,9 +50,9 @@ entity control is
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jalr_o : out std_logic;
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ecall_o : out std_logic;
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-- mem access
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memrd_o : out std_logic;
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memwr_o : out std_logic;
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byte_en_o : out std_logic_vector(1 downto 0);
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mem_rd_o : out std_logic;
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mem_wr_o : out std_logic;
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mem_ben_o : out std_logic_vector(1 downto 0);
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mem_usgn_o : out std_logic; -- unsigned data
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-- U type
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load_upimm_o : out std_logic;
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@ -102,9 +102,9 @@ architecture arch of control is
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constant SYS_CSRRCI : std_logic_vector(2 downto 0) := "111";
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-- auxiliar signals
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signal memwr_w : std_logic;
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signal memrd_w : std_logic;
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signal memreq_w : std_logic;
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signal mem_wr_w : std_logic;
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signal mem_rd_w : std_logic;
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signal mem_req_w : std_logic;
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-- opcodes
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@ -121,7 +121,7 @@ begin
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imem_req_o <= '1' when proc_status_r = STAT_REQ_INSTR else '0';
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-- STAT_DMEM_STALL
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memreq_w <= memrd_w or memwr_w;
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mem_req_w <= mem_rd_w or mem_wr_w;
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dmem_req_o <= '1' when proc_status_r = STAT_DMEM_STALL else '0';
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-- STAT_UPDATE_PC
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@ -140,7 +140,7 @@ begin
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end if;
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end process;
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PROC_NEXT_STATUS : process(proc_status_r, start_i, imem_gnt_i, imem_err_i, dmem_outofrange_i, memreq_w, dmem_gnt_i)
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PROC_NEXT_STATUS : process(proc_status_r, start_i, imem_gnt_i, imem_err_i, dmem_err_i, mem_req_w, dmem_gnt_i)
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begin
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case proc_status_r is
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@ -163,14 +163,14 @@ begin
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end if;
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when STAT_RUN =>
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if memreq_w = '1' then
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if mem_req_w = '1' then
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next_proc_status_w <= STAT_DMEM_STALL;
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else
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next_proc_status_w <= STAT_UPDATE_PC;
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end if;
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when STAT_DMEM_STALL =>
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if dmem_outofrange_i = '1' then -- or dmem_sbu_i = '1' or dmem_dbu_i = '1' then
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if dmem_err_i = '1' then -- or dmem_sbu_i = '1' or dmem_dbu_i = '1' then
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next_proc_status_w <= STAT_TRAP;
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elsif dmem_gnt_i = '1' then
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next_proc_status_w <= STAT_UPDATE_PC;
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@ -262,11 +262,11 @@ begin
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ecall_o <= '0'; -- '1' when instr_format_w = I_system else
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------------------------------ MEM ACCESS ---------------------------------
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memrd_w <= '1' when instr_format_w = I_load else '0';
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memrd_o <= memrd_w;
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memwr_w <= '1' when instr_format_w = S else '0';
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memwr_o <= memwr_w;
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byte_en_o <= funct3_i(1 downto 0) when funct3_i(1) = '0' else "11"; -- byte or halfword -- else word
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mem_rd_w <= '1' when instr_format_w = I_load else '0';
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mem_rd_o <= mem_rd_w;
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mem_wr_w <= '1' when instr_format_w = S else '0';
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mem_wr_o <= mem_wr_w;
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mem_ben_o <= funct3_i(1 downto 0) when funct3_i(1) = '0' else "11"; -- byte or halfword -- else word
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mem_usgn_o <= funct3_i(2);
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-------------------------------- U type -----------------------------------
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@ -10,12 +10,12 @@ entity control_tmr is
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port (
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-- input ports
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-- processor status
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imem_gnt_i : in std_logic;
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imem_err_i : in std_logic;
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dmem_gnt_i : in std_logic;
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dmem_outofrange_i : in std_logic;
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dmem_sbu_i : in std_logic;
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dmem_dbu_i : in std_logic;
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imem_gnt_i : in std_logic;
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imem_err_i : in std_logic;
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dmem_gnt_i : in std_logic;
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dmem_err_i : in std_logic;
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dmem_sbu_i : in std_logic;
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dmem_dbu_i : in std_logic;
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-- instruction decode
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opcode_i : in std_logic_vector(6 downto 0);
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@ -49,7 +49,7 @@ entity control_tmr is
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imm_shamt_o : out std_logic;
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imm_up_o : out std_logic;
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-- register bank
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regwr_o : out std_logic;
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regwr_o : out std_logic;
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-- control transfer
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inv_branch_o : out std_logic;
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branch_o : out std_logic;
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@ -57,9 +57,9 @@ entity control_tmr is
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jalr_o : out std_logic;
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ecall_o : out std_logic;
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-- mem access
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memrd_o : out std_logic;
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memwr_o : out std_logic;
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byte_en_o : out std_logic_vector(1 downto 0);
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mem_rd_o : out std_logic;
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mem_wr_o : out std_logic;
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mem_ben_o : out std_logic_vector(1 downto 0);
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mem_usgn_o : out std_logic; -- unsigned data
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-- U type
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load_upimm_o : out std_logic;
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@ -87,8 +87,8 @@ architecture arch of control_tmr is
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signal jump_w : tmr_std_logic_t;
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signal jalr_w : tmr_std_logic_t;
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signal ecall_w : tmr_std_logic_t;
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signal memrd_w : tmr_std_logic_t;
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signal memwr_w : tmr_std_logic_t;
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signal mem_rd_w : tmr_std_logic_t;
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signal mem_wr_w : tmr_std_logic_t;
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signal mem_usgn_w : tmr_std_logic_t;
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signal load_upimm_w : tmr_std_logic_t;
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signal auipc_w : tmr_std_logic_t;
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@ -110,8 +110,8 @@ architecture arch of control_tmr is
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signal corr_jump_w : std_logic;
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signal corr_jalr_w : std_logic;
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signal corr_ecall_w : std_logic;
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signal corr_memrd_w : std_logic;
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signal corr_memwr_w : std_logic;
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signal corr_mem_rd_w : std_logic;
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signal corr_mem_wr_w : std_logic;
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signal corr_mem_usgn_w : std_logic;
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signal corr_load_upimm_w : std_logic;
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signal corr_auipc_w : std_logic;
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@ -133,8 +133,8 @@ architecture arch of control_tmr is
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signal error_jump_w : std_logic;
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signal error_jalr_w : std_logic;
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signal error_ecall_w : std_logic;
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signal error_memrd_w : std_logic;
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signal error_memwr_w : std_logic;
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signal error_mem_rd_w : std_logic;
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signal error_mem_wr_w : std_logic;
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signal error_mem_usgn_w : std_logic;
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signal error_load_upimm_w : std_logic;
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signal error_auipc_w : std_logic;
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@ -149,9 +149,9 @@ architecture arch of control_tmr is
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signal error_aluop_w : std_logic;
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type tmr_std_logic_2_t is array(2 downto 0) of std_logic_vector(1 downto 0);
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signal byte_en_w : tmr_std_logic_2_t;
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signal corr_byte_en_w : std_logic_vector(1 downto 0);
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signal error_byte_en_w : std_logic;
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signal mem_ben_w : tmr_std_logic_2_t;
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signal corr_mem_ben_w : std_logic_vector(1 downto 0);
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signal error_mem_ben_w : std_logic;
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begin
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gen_TMR : for i in 2 downto 0 generate
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@ -170,43 +170,43 @@ begin
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begin
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control_i : control
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port map (
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imem_gnt_i => imem_gnt_i,
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imem_err_i => imem_err_i,
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dmem_gnt_i => dmem_gnt_i,
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dmem_outofrange_i => dmem_outofrange_i,
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dmem_sbu_i => dmem_sbu_i,
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dmem_dbu_i => dmem_dbu_i,
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opcode_i => opcode_i,
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funct3_i => funct3_i,
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funct7_i => funct7_i,
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funct12_i => funct12_i,
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rstn_i => rstn_i,
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clk_i => clk_i,
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start_i => start_i,
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imem_req_o => imem_req_w(i),
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dmem_req_o => dmem_req_w(i),
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update_pc_o => update_pc_w(i),
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trap_o => trap_w(i),
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aluop_o => aluop_w(i),
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alusrc_imm_o => alusrc_imm_w(i),
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imm_shamt_o => imm_shamt_w(i),
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imm_up_o => imm_up_w(i),
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regwr_o => regwr_w(i),
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inv_branch_o => inv_branch_w(i),
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branch_o => branch_w(i),
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jump_o => jump_w(i),
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jalr_o => jalr_w(i),
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ecall_o => ecall_w(i),
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memrd_o => memrd_w(i),
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memwr_o => memwr_w(i),
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byte_en_o => byte_en_w(i),
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mem_usgn_o => mem_usgn_w(i),
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load_upimm_o => load_upimm_w(i),
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auipc_o => auipc_w(i),
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csr_enable_o => csr_enable_w(i),
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csr_source_imm_o => csr_source_imm_w(i),
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csr_maskop_o => csr_maskop_w(i),
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csr_clearop_o => csr_clearop_w(i)
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imem_gnt_i => imem_gnt_i,
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imem_err_i => imem_err_i,
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dmem_gnt_i => dmem_gnt_i,
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dmem_err_i => dmem_err_i,
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dmem_sbu_i => dmem_sbu_i,
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dmem_dbu_i => dmem_dbu_i,
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opcode_i => opcode_i,
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funct3_i => funct3_i,
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funct7_i => funct7_i,
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funct12_i => funct12_i,
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rstn_i => rstn_i,
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clk_i => clk_i,
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start_i => start_i,
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imem_req_o => imem_req_w(i),
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dmem_req_o => dmem_req_w(i),
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update_pc_o => update_pc_w(i),
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trap_o => trap_w(i),
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aluop_o => aluop_w(i),
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alusrc_imm_o => alusrc_imm_w(i),
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imm_shamt_o => imm_shamt_w(i),
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imm_up_o => imm_up_w(i),
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regwr_o => regwr_w(i),
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inv_branch_o => inv_branch_w(i),
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branch_o => branch_w(i),
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jump_o => jump_w(i),
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jalr_o => jalr_w(i),
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ecall_o => ecall_w(i),
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mem_rd_o => mem_rd_w(i),
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mem_wr_o => mem_wr_w(i),
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mem_ben_o => mem_ben_w(i),
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mem_usgn_o => mem_usgn_w(i),
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load_upimm_o => load_upimm_w(i),
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auipc_o => auipc_w(i),
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csr_enable_o => csr_enable_w(i),
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csr_source_imm_o => csr_source_imm_w(i),
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csr_maskop_o => csr_maskop_w(i),
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csr_clearop_o => csr_clearop_w(i)
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);
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end generate;
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@ -224,9 +224,9 @@ begin
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corr_jump_w <= ( jump_w(2) and jump_w(1)) or ( jump_w(2) and jump_w(0)) or ( jump_w(1) and jump_w(0));
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corr_jalr_w <= ( jalr_w(2) and jalr_w(1)) or ( jalr_w(2) and jalr_w(0)) or ( jalr_w(1) and jalr_w(0));
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corr_ecall_w <= ( ecall_w(2) and ecall_w(1)) or ( ecall_w(2) and ecall_w(0)) or ( ecall_w(1) and ecall_w(0));
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corr_memrd_w <= ( memrd_w(2) and memrd_w(1)) or ( memrd_w(2) and memrd_w(0)) or ( memrd_w(1) and memrd_w(0));
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corr_memwr_w <= ( memwr_w(2) and memwr_w(1)) or ( memwr_w(2) and memwr_w(0)) or ( memwr_w(1) and memwr_w(0));
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corr_byte_en_w <= ( byte_en_w(2) and byte_en_w(1)) or ( byte_en_w(2) and byte_en_w(0)) or ( byte_en_w(1) and byte_en_w(0));
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corr_mem_rd_w <= ( mem_rd_w(2) and mem_rd_w(1)) or ( mem_rd_w(2) and mem_rd_w(0)) or ( mem_rd_w(1) and mem_rd_w(0));
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corr_mem_wr_w <= ( mem_wr_w(2) and mem_wr_w(1)) or ( mem_wr_w(2) and mem_wr_w(0)) or ( mem_wr_w(1) and mem_wr_w(0));
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corr_mem_ben_w <= ( mem_ben_w(2) and mem_ben_w(1)) or ( mem_ben_w(2) and mem_ben_w(0)) or ( mem_ben_w(1) and mem_ben_w(0));
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corr_mem_usgn_w <= ( mem_usgn_w(2) and mem_usgn_w(1)) or ( mem_usgn_w(2) and mem_usgn_w(0)) or ( mem_usgn_w(1) and mem_usgn_w(0));
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corr_load_upimm_w <= ( load_upimm_w(2) and load_upimm_w(1)) or ( load_upimm_w(2) and load_upimm_w(0)) or ( load_upimm_w(1) and load_upimm_w(0));
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corr_auipc_w <= ( auipc_w(2) and auipc_w(1)) or ( auipc_w(2) and auipc_w(0)) or ( auipc_w(1) and auipc_w(0));
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@ -249,9 +249,9 @@ begin
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error_jump_w <= ( jump_w(2) xor jump_w(1)) or ( jump_w(2) xor jump_w(0)) or ( jump_w(1) xor jump_w(0));
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error_jalr_w <= ( jalr_w(2) xor jalr_w(1)) or ( jalr_w(2) xor jalr_w(0)) or ( jalr_w(1) xor jalr_w(0));
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error_ecall_w <= ( ecall_w(2) xor ecall_w(1)) or ( ecall_w(2) xor ecall_w(0)) or ( ecall_w(1) xor ecall_w(0));
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error_memrd_w <= ( memrd_w(2) xor memrd_w(1)) or ( memrd_w(2) xor memrd_w(0)) or ( memrd_w(1) xor memrd_w(0));
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error_memwr_w <= ( memwr_w(2) xor memwr_w(1)) or ( memwr_w(2) xor memwr_w(0)) or ( memwr_w(1) xor memwr_w(0));
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error_byte_en_w <= or_reduce(( byte_en_w(2) xor byte_en_w(1)) or ( byte_en_w(2) xor byte_en_w(0)) or ( byte_en_w(1) xor byte_en_w(0)));
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error_mem_rd_w <= ( mem_rd_w(2) xor mem_rd_w(1)) or ( mem_rd_w(2) xor mem_rd_w(0)) or ( mem_rd_w(1) xor mem_rd_w(0));
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error_mem_wr_w <= ( mem_wr_w(2) xor mem_wr_w(1)) or ( mem_wr_w(2) xor mem_wr_w(0)) or ( mem_wr_w(1) xor mem_wr_w(0));
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error_mem_ben_w <= or_reduce((mem_ben_w(2) xor mem_ben_w(1)) or (mem_ben_w(2) xor mem_ben_w(0)) or ( mem_ben_w(1) xor mem_ben_w(0)));
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error_mem_usgn_w <= ( mem_usgn_w(2) xor mem_usgn_w(1)) or ( mem_usgn_w(2) xor mem_usgn_w(0)) or ( mem_usgn_w(1) xor mem_usgn_w(0));
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error_load_upimm_w <= ( load_upimm_w(2) xor load_upimm_w(1)) or ( load_upimm_w(2) xor load_upimm_w(0)) or ( load_upimm_w(1) xor load_upimm_w(0));
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error_auipc_w <= ( auipc_w(2) xor auipc_w(1)) or ( auipc_w(2) xor auipc_w(0)) or ( auipc_w(1) xor auipc_w(0));
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@ -265,8 +265,8 @@ begin
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error_trap_w or error_aluop_w or error_alusrc_imm_w or
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error_imm_shamt_w or error_imm_up_w or error_regwr_w or
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error_inv_branch_w or error_branch_w or error_jump_w or
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error_jalr_w or error_ecall_w or error_memrd_w or
|
||||
error_memwr_w or error_byte_en_w or error_mem_usgn_w or
|
||||
error_jalr_w or error_ecall_w or error_mem_rd_w or
|
||||
error_mem_wr_w or error_mem_ben_w or error_mem_usgn_w or
|
||||
error_load_upimm_w or error_auipc_w or error_csr_enable_w or
|
||||
error_csr_source_imm_w or error_csr_maskop_w or error_csr_clearop_w;
|
||||
|
||||
|
|
@ -285,9 +285,9 @@ begin
|
|||
jump_o <= corr_jump_w when correct_error_i = '1' else jump_w (0);
|
||||
jalr_o <= corr_jalr_w when correct_error_i = '1' else jalr_w (0);
|
||||
ecall_o <= corr_ecall_w when correct_error_i = '1' else ecall_w (0);
|
||||
memrd_o <= corr_memrd_w when correct_error_i = '1' else memrd_w (0);
|
||||
memwr_o <= corr_memwr_w when correct_error_i = '1' else memwr_w (0);
|
||||
byte_en_o <= corr_byte_en_w when correct_error_i = '1' else byte_en_w (0);
|
||||
mem_rd_o <= corr_mem_rd_w when correct_error_i = '1' else mem_rd_w (0);
|
||||
mem_wr_o <= corr_mem_wr_w when correct_error_i = '1' else mem_wr_w (0);
|
||||
mem_ben_o <= corr_mem_ben_w when correct_error_i = '1' else mem_ben_w (0);
|
||||
mem_usgn_o <= corr_mem_usgn_w when correct_error_i = '1' else mem_usgn_w (0);
|
||||
load_upimm_o <= corr_load_upimm_w when correct_error_i = '1' else load_upimm_w (0);
|
||||
auipc_o <= corr_auipc_w when correct_error_i = '1' else auipc_w (0);
|
||||
|
|
|
|||
221
hdl/harv.vhd
221
hdl/harv.vhd
|
|
@ -23,24 +23,24 @@ entity harv is
|
|||
poweron_rstn_i : in std_logic;
|
||||
wdt_rstn_i : in std_logic;
|
||||
-- INSTRUCTION MEMORY
|
||||
imem_instr_i : in std_logic_vector(31 downto 0);
|
||||
imem_instr_i : in std_logic_vector(31 downto 0);
|
||||
imem_pc_o : out std_logic_vector(31 downto 0);
|
||||
imem_req_o : out std_logic;
|
||||
imem_gnt_i : in std_logic;
|
||||
imem_err_i : in std_logic;
|
||||
imem_gnt_i : in std_logic;
|
||||
imem_err_i : in std_logic;
|
||||
-- DATA MEMORY
|
||||
hard_dmem_o : out std_logic;
|
||||
dmem_data_i : in std_logic_vector(31 downto 0);
|
||||
dmem_req_o : out std_logic;
|
||||
dmem_wren_o : out std_logic;
|
||||
dmem_gnt_i : in std_logic;
|
||||
dmem_outofrange_i : in std_logic;
|
||||
dmem_sbu_i : in std_logic;
|
||||
dmem_dbu_i : in std_logic;
|
||||
dmem_byte_en_o : out std_logic_vector(1 downto 0);
|
||||
dmem_usgn_dat_o : out std_logic;
|
||||
dmem_data_o : out std_logic_vector(31 downto 0);
|
||||
dmem_addr_o : out std_logic_vector(31 downto 0)
|
||||
hard_dmem_o : out std_logic;
|
||||
dmem_req_o : out std_logic;
|
||||
dmem_wren_o : out std_logic;
|
||||
dmem_ben_o : out std_logic_vector(1 downto 0);
|
||||
dmem_usgn_o : out std_logic;
|
||||
dmem_addr_o : out std_logic_vector(31 downto 0);
|
||||
dmem_wdata_o : out std_logic_vector(31 downto 0);
|
||||
dmem_gnt_i : in std_logic;
|
||||
dmem_err_i : in std_logic;
|
||||
dmem_sbu_i : in std_logic;
|
||||
dmem_dbu_i : in std_logic;
|
||||
dmem_rdata_i : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
|
|
@ -80,9 +80,9 @@ architecture arch of harv is
|
|||
signal ctl_jump_w : std_logic;
|
||||
signal ctl_jalr_w : std_logic;
|
||||
signal ctl_ecall_w : std_logic;
|
||||
signal ctl_memrd_w : std_logic;
|
||||
signal ctl_memwr_w : std_logic;
|
||||
signal ctl_byte_en_w : std_logic_vector(1 downto 0);
|
||||
signal ctl_mem_rd_w : std_logic;
|
||||
signal ctl_mem_wr_w : std_logic;
|
||||
signal ctl_mem_ben_w : std_logic_vector(1 downto 0);
|
||||
signal ctl_mem_usgn_w : std_logic;
|
||||
signal ctl_load_upimm_w : std_logic;
|
||||
signal ctl_auipc_w : std_logic;
|
||||
|
|
@ -92,9 +92,9 @@ architecture arch of harv is
|
|||
signal ctl_csr_clearop_w : std_logic;
|
||||
signal instr_w : std_logic_vector(31 downto 0);
|
||||
------------- REGFILE -------------
|
||||
signal data_wr_w : std_logic_vector(31 downto 0);
|
||||
signal reg_data1_w : std_logic_vector(31 downto 0);
|
||||
signal reg_data2_w : std_logic_vector(31 downto 0);
|
||||
signal data_wr_w : std_logic_vector(31 downto 0);
|
||||
signal reg_data1_w : std_logic_vector(31 downto 0);
|
||||
signal reg_data2_w : std_logic_vector(31 downto 0);
|
||||
-------------- ALU -----------------
|
||||
signal alu_data1_w : std_logic_vector(31 downto 0);
|
||||
signal alu_data2_w : std_logic_vector(31 downto 0);
|
||||
|
|
@ -115,8 +115,8 @@ architecture arch of harv is
|
|||
signal reg2_sbu_w : std_logic;
|
||||
signal reg2_dbu_w : std_logic;
|
||||
-- signal pc_cen_w : std_logic;
|
||||
signal pc_sbu_w : std_logic;
|
||||
signal pc_dbu_w : std_logic;
|
||||
signal pc_sbu_w : std_logic;
|
||||
signal pc_dbu_w : std_logic;
|
||||
|
||||
signal control_err_w : std_logic;
|
||||
signal alu_err_w : std_logic;
|
||||
|
|
@ -131,25 +131,25 @@ begin
|
|||
HAMMING_PC => HAMMING_PC
|
||||
)
|
||||
port map (
|
||||
branch_imm_i => imm_branch_w,
|
||||
jump_imm_i => alu_data_w,
|
||||
inv_branch_i => ctl_inv_branch_w,
|
||||
branch_i => ctl_branch_w,
|
||||
zero_i => alu_zero_w,
|
||||
jump_i => ctl_jump_w,
|
||||
ecall_i => ctl_ecall_w,
|
||||
branch_imm_i => imm_branch_w,
|
||||
jump_imm_i => alu_data_w,
|
||||
inv_branch_i => ctl_inv_branch_w,
|
||||
branch_i => ctl_branch_w,
|
||||
zero_i => alu_zero_w,
|
||||
jump_i => ctl_jump_w,
|
||||
ecall_i => ctl_ecall_w,
|
||||
correct_error_i => hard_pc_w,
|
||||
instr_gnt_i => imem_gnt_i,
|
||||
instr_i => imem_instr_i,
|
||||
rstn_i => rstn_i,
|
||||
clk_i => clk_w,
|
||||
update_pc_i => update_pc_w,
|
||||
trap_i => trap_w,
|
||||
instr_o => instr_w,
|
||||
sbu_o => pc_sbu_w,
|
||||
dbu_o => pc_dbu_w,
|
||||
pc_o => if_pc_w,
|
||||
pc_4_o => if_pc_4_w
|
||||
instr_gnt_i => imem_gnt_i,
|
||||
instr_i => imem_instr_i,
|
||||
rstn_i => rstn_i,
|
||||
clk_i => clk_w,
|
||||
update_pc_i => update_pc_w,
|
||||
trap_i => trap_w,
|
||||
instr_o => instr_w,
|
||||
sbu_o => pc_sbu_w,
|
||||
dbu_o => pc_dbu_w,
|
||||
pc_o => if_pc_w,
|
||||
pc_4_o => if_pc_4_w
|
||||
);
|
||||
imem_pc_o <= if_pc_w;
|
||||
|
||||
|
|
@ -171,20 +171,20 @@ begin
|
|||
control_i : control_tmr
|
||||
port map (
|
||||
start_i => start_i,
|
||||
imem_gnt_i => imem_gnt_i,
|
||||
imem_err_i => imem_err_i,
|
||||
dmem_gnt_i => dmem_gnt_i,
|
||||
dmem_outofrange_i => dmem_outofrange_i,
|
||||
dmem_sbu_i => dmem_sbu_i and dmem_gnt_i and not ctl_memwr_w,
|
||||
dmem_dbu_i => dmem_dbu_i and dmem_gnt_i and not ctl_memwr_w,
|
||||
imem_gnt_i => imem_gnt_i,
|
||||
imem_err_i => imem_err_i,
|
||||
dmem_gnt_i => dmem_gnt_i,
|
||||
dmem_err_i => dmem_err_i,
|
||||
dmem_sbu_i => dmem_sbu_i and dmem_gnt_i and ctl_mem_rd_w,
|
||||
dmem_dbu_i => dmem_dbu_i and dmem_gnt_i and ctl_mem_rd_w,
|
||||
opcode_i => opcode_w,
|
||||
funct3_i => funct3_w,
|
||||
funct7_i => funct7_w,
|
||||
funct12_i => funct12_w,
|
||||
rstn_i => rstn_i,
|
||||
clk_i => clk_i,
|
||||
imem_req_o => imem_req_o,
|
||||
dmem_req_o => dmem_req_o,
|
||||
imem_req_o => imem_req_o,
|
||||
dmem_req_o => dmem_req_o,
|
||||
update_pc_o => update_pc_w,
|
||||
trap_o => trap_w,
|
||||
aluop_o => ctl_aluop_w,
|
||||
|
|
@ -197,9 +197,9 @@ begin
|
|||
jump_o => ctl_jump_w,
|
||||
jalr_o => ctl_jalr_w,
|
||||
ecall_o => ctl_ecall_w,
|
||||
memrd_o => ctl_memrd_w,
|
||||
memwr_o => ctl_memwr_w,
|
||||
byte_en_o => ctl_byte_en_w,
|
||||
mem_rd_o => ctl_mem_rd_w,
|
||||
mem_wr_o => ctl_mem_wr_w,
|
||||
mem_ben_o => ctl_mem_ben_w,
|
||||
mem_usgn_o => ctl_mem_usgn_w,
|
||||
load_upimm_o => ctl_load_upimm_w,
|
||||
auipc_o => ctl_auipc_w,
|
||||
|
|
@ -215,57 +215,57 @@ begin
|
|||
control_i : control
|
||||
port map (
|
||||
-- processor status
|
||||
start_i => start_i,
|
||||
imem_gnt_i => imem_gnt_i,
|
||||
imem_err_i => imem_err_i,
|
||||
dmem_gnt_i => dmem_gnt_i,
|
||||
dmem_outofrange_i => dmem_outofrange_i,
|
||||
dmem_sbu_i => dmem_sbu_i,
|
||||
dmem_dbu_i => dmem_dbu_i,
|
||||
start_i => start_i,
|
||||
imem_gnt_i => imem_gnt_i,
|
||||
imem_err_i => imem_err_i,
|
||||
dmem_gnt_i => dmem_gnt_i,
|
||||
dmem_err_i => dmem_err_i,
|
||||
dmem_sbu_i => dmem_sbu_i,
|
||||
dmem_dbu_i => dmem_dbu_i,
|
||||
|
||||
-- instruction decode
|
||||
opcode_i => opcode_w,
|
||||
funct3_i => funct3_w,
|
||||
funct7_i => funct7_w,
|
||||
funct12_i => funct12_w,
|
||||
opcode_i => opcode_w,
|
||||
funct3_i => funct3_w,
|
||||
funct7_i => funct7_w,
|
||||
funct12_i => funct12_w,
|
||||
|
||||
rstn_i => rstn_i,
|
||||
clk_i => clk_i,
|
||||
rstn_i => rstn_i,
|
||||
clk_i => clk_i,
|
||||
|
||||
-- processor status
|
||||
imem_req_o => imem_req_o,
|
||||
dmem_req_o => dmem_req_o,
|
||||
imem_req_o => imem_req_o,
|
||||
dmem_req_o => dmem_req_o,
|
||||
update_pc_o => update_pc_w,
|
||||
trap_o => trap_w,
|
||||
|
||||
-- instruction decode
|
||||
aluop_o => ctl_aluop_w,
|
||||
alusrc_imm_o => ctl_alusrc_imm_w,
|
||||
imm_shamt_o => ctl_imm_shamt_w,
|
||||
imm_up_o => ctl_imm_up_w,
|
||||
regwr_o => ctl_regwr_w,
|
||||
inv_branch_o => ctl_inv_branch_w,
|
||||
branch_o => ctl_branch_w,
|
||||
jump_o => ctl_jump_w,
|
||||
jalr_o => ctl_jalr_w,
|
||||
ecall_o => ctl_ecall_w,
|
||||
memrd_o => ctl_memrd_w,
|
||||
memwr_o => ctl_memwr_w,
|
||||
byte_en_o => ctl_byte_en_w,
|
||||
mem_usgn_o => ctl_mem_usgn_w,
|
||||
load_upimm_o => ctl_load_upimm_w,
|
||||
auipc_o => ctl_auipc_w,
|
||||
csr_enable_o => ctl_csr_enable_w,
|
||||
csr_source_imm_o => ctl_csr_source_imm_w,
|
||||
csr_maskop_o => ctl_csr_maskop_w,
|
||||
csr_clearop_o => ctl_csr_clearop_w
|
||||
aluop_o => ctl_aluop_w,
|
||||
alusrc_imm_o => ctl_alusrc_imm_w,
|
||||
imm_shamt_o => ctl_imm_shamt_w,
|
||||
imm_up_o => ctl_imm_up_w,
|
||||
regwr_o => ctl_regwr_w,
|
||||
inv_branch_o => ctl_inv_branch_w,
|
||||
branch_o => ctl_branch_w,
|
||||
jump_o => ctl_jump_w,
|
||||
jalr_o => ctl_jalr_w,
|
||||
ecall_o => ctl_ecall_w,
|
||||
mem_rd_o => ctl_mem_rd_w,
|
||||
mem_wr_o => ctl_mem_wr_w,
|
||||
mem_ben_o => ctl_mem_ben_w,
|
||||
mem_usgn_o => ctl_mem_usgn_w,
|
||||
load_upimm_o => ctl_load_upimm_w,
|
||||
auipc_o => ctl_auipc_w,
|
||||
csr_enable_o => ctl_csr_enable_w,
|
||||
csr_source_imm_o => ctl_csr_source_imm_w,
|
||||
csr_maskop_o => ctl_csr_maskop_w,
|
||||
csr_clearop_o => ctl_csr_clearop_w
|
||||
);
|
||||
end generate;
|
||||
|
||||
data_wr_w <= dmem_data_i when ctl_memrd_w = '1' else
|
||||
imm_w when ctl_load_upimm_w = '1' else
|
||||
if_pc_4_w when ctl_jump_w = '1' else
|
||||
csr_rdata_w when ctl_csr_enable_w = '1' else
|
||||
data_wr_w <= dmem_rdata_i when ctl_mem_rd_w = '1' else
|
||||
imm_w when ctl_load_upimm_w = '1' else
|
||||
if_pc_4_w when ctl_jump_w = '1' else
|
||||
csr_rdata_w when ctl_csr_enable_w = '1' else
|
||||
alu_data_w;
|
||||
|
||||
regfile_i : regfile
|
||||
|
|
@ -288,27 +288,26 @@ begin
|
|||
data2_o => reg_data2_w
|
||||
);
|
||||
|
||||
imm_sel_w <= ctl_imm_shamt_w & ctl_imm_up_w & ctl_memwr_w & (ctl_jump_w and not ctl_jalr_w);
|
||||
imm_sel_w <= ctl_imm_shamt_w & ctl_imm_up_w & ctl_mem_wr_w & (ctl_jump_w and not ctl_jalr_w);
|
||||
|
||||
with imm_sel_w select imm_w <=
|
||||
std_logic_vector(resize(unsigned(imm_shamt_w), 32)) when "1000", -- ctl_imm_shamt_w = '1' else
|
||||
std_logic_vector(shift_left(resize(signed(imm_up_w), 32), 12)) when "0100", -- ctl_imm_up_w = '1' else
|
||||
std_logic_vector(resize(signed(imm_store_w), 32)) when "0010", -- ctl_memwr_w = '1' else
|
||||
std_logic_vector(resize(signed(imm_store_w), 32)) when "0010", -- ctl_mem_wr_w = '1' else
|
||||
std_logic_vector(resize(signed(imm_upj_w), 32)) when "0001", -- (ctl_jump_w and not ctl_jalr_w) = '1' else
|
||||
std_logic_vector(resize(signed(imm_i_w), 32)) when others;
|
||||
|
||||
alu_data1_w <= if_pc_w when (ctl_auipc_w or (ctl_jump_w and not ctl_jalr_w)) = '1' else
|
||||
reg_data1_w;
|
||||
alu_data2_w <= imm_w when ctl_alusrc_imm_w = '1' else reg_data2_w;
|
||||
alu_data1_w <= if_pc_w when (ctl_auipc_w or (ctl_jump_w and not ctl_jalr_w)) = '1' else reg_data1_w;
|
||||
alu_data2_w <= imm_w when ctl_alusrc_imm_w = '1' else reg_data2_w;
|
||||
|
||||
gen_ft_alu : if TMR_ALU generate
|
||||
alu_i : alu_tmr
|
||||
port map (
|
||||
data1_i => alu_data1_w,
|
||||
data2_i => alu_data2_w,
|
||||
operation_i => ctl_aluop_w,
|
||||
zero_o => alu_zero_w,
|
||||
data_o => alu_data_w,
|
||||
data1_i => alu_data1_w,
|
||||
data2_i => alu_data2_w,
|
||||
operation_i => ctl_aluop_w,
|
||||
zero_o => alu_zero_w,
|
||||
data_o => alu_data_w,
|
||||
correct_error_i => hard_alu_w,
|
||||
error_o => alu_err_w
|
||||
);
|
||||
|
|
@ -325,10 +324,10 @@ begin
|
|||
end generate;
|
||||
|
||||
---------- CSR registers ---------
|
||||
csr_ucause_w <= x"00000010" when dmem_sbu_i = '1' else -- SBU
|
||||
x"00000020" when dmem_dbu_i = '1' else -- DBU
|
||||
x"00000007" when ctl_memwr_w = '1' else -- store address fault
|
||||
x"00000005"; -- load address fault
|
||||
csr_ucause_w <= x"00000010" when dmem_sbu_i = '1' else -- SBU
|
||||
x"00000020" when dmem_dbu_i = '1' else -- DBU
|
||||
x"00000007" when ctl_mem_wr_w = '1' else -- store address fault
|
||||
x"00000005"; -- when ctl_mem_rd_w = '1' -- load address fault
|
||||
csr_i : csr
|
||||
generic map (
|
||||
TMR_CONTROL => TMR_CONTROL,
|
||||
|
|
@ -366,7 +365,7 @@ begin
|
|||
pc_cen_i => update_pc_w,
|
||||
pc_sbu_i => pc_sbu_w,
|
||||
pc_dbu_i => pc_dbu_w,
|
||||
dmem_cen_i => dmem_gnt_i and not ctl_memwr_w,
|
||||
dmem_cen_i => dmem_gnt_i and not ctl_mem_wr_w,
|
||||
dmem_sbu_i => dmem_sbu_i,
|
||||
dmem_dbu_i => dmem_dbu_i,
|
||||
control_cen_i => '1',
|
||||
|
|
@ -387,10 +386,10 @@ begin
|
|||
-------- DATA MEMORY --------
|
||||
-- output signals
|
||||
-- dmem_req_o is set by the control unit
|
||||
dmem_wren_o <= ctl_memwr_w;
|
||||
dmem_byte_en_o <= ctl_byte_en_w;
|
||||
dmem_usgn_dat_o <= ctl_mem_usgn_w;
|
||||
dmem_data_o <= reg_data2_w;
|
||||
dmem_addr_o <= alu_data_w;
|
||||
dmem_wren_o <= ctl_mem_wr_w;
|
||||
dmem_ben_o <= ctl_mem_ben_w;
|
||||
dmem_usgn_o <= ctl_mem_usgn_w;
|
||||
dmem_wdata_o <= reg_data2_w;
|
||||
dmem_addr_o <= alu_data_w;
|
||||
|
||||
end architecture;
|
||||
|
|
|
|||
212
hdl/harv_pkg.vhd
212
hdl/harv_pkg.vhd
|
|
@ -20,85 +20,85 @@ package harv_pkg is
|
|||
------- COMPONENTS -----
|
||||
component harv
|
||||
generic (
|
||||
PROGRAM_START_ADDR : std_logic_vector(31 downto 0);
|
||||
TRAP_HANDLER_ADDR : std_logic_vector(31 downto 0);
|
||||
TMR_CONTROL : boolean;
|
||||
TMR_ALU : boolean;
|
||||
HAMMING_REGFILE : boolean;
|
||||
HAMMING_PC : boolean
|
||||
PROGRAM_START_ADDR : std_logic_vector(31 downto 0);
|
||||
TRAP_HANDLER_ADDR : std_logic_vector(31 downto 0);
|
||||
TMR_CONTROL : boolean;
|
||||
TMR_ALU : boolean;
|
||||
HAMMING_REGFILE : boolean;
|
||||
HAMMING_PC : boolean
|
||||
);
|
||||
port (
|
||||
rstn_i : in std_logic;
|
||||
clk_i : in std_logic;
|
||||
start_i : in std_logic;
|
||||
poweron_rstn_i : in std_logic;
|
||||
wdt_rstn_i : in std_logic;
|
||||
imem_instr_i : in std_logic_vector(31 downto 0);
|
||||
imem_pc_o : out std_logic_vector(31 downto 0);
|
||||
imem_req_o : out std_logic;
|
||||
imem_gnt_i : in std_logic;
|
||||
imem_err_i : in std_logic;
|
||||
hard_dmem_o : out std_logic;
|
||||
dmem_data_i : in std_logic_vector(31 downto 0);
|
||||
dmem_req_o : out std_logic;
|
||||
dmem_wren_o : out std_logic;
|
||||
dmem_gnt_i : in std_logic;
|
||||
dmem_outofrange_i : in std_logic;
|
||||
dmem_sbu_i : in std_logic;
|
||||
dmem_dbu_i : in std_logic;
|
||||
dmem_byte_en_o : out std_logic_vector(1 downto 0);
|
||||
dmem_usgn_dat_o : out std_logic;
|
||||
dmem_data_o : out std_logic_vector(31 downto 0);
|
||||
dmem_addr_o : out std_logic_vector(31 downto 0)
|
||||
rstn_i : in std_logic;
|
||||
clk_i : in std_logic;
|
||||
start_i : in std_logic;
|
||||
poweron_rstn_i : in std_logic;
|
||||
wdt_rstn_i : in std_logic;
|
||||
imem_instr_i : in std_logic_vector(31 downto 0);
|
||||
imem_pc_o : out std_logic_vector(31 downto 0);
|
||||
imem_req_o : out std_logic;
|
||||
imem_gnt_i : in std_logic;
|
||||
imem_err_i : in std_logic;
|
||||
hard_dmem_o : out std_logic;
|
||||
dmem_req_o : out std_logic;
|
||||
dmem_wren_o : out std_logic;
|
||||
dmem_ben_o : out std_logic_vector(1 downto 0);
|
||||
dmem_usgn_o : out std_logic;
|
||||
dmem_addr_o : out std_logic_vector(31 downto 0);
|
||||
dmem_wdata_o : out std_logic_vector(31 downto 0);
|
||||
dmem_gnt_i : in std_logic;
|
||||
dmem_err_i : in std_logic;
|
||||
dmem_sbu_i : in std_logic;
|
||||
dmem_dbu_i : in std_logic;
|
||||
dmem_rdata_i : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component harv;
|
||||
|
||||
component control
|
||||
port (
|
||||
imem_gnt_i : in std_logic;
|
||||
imem_err_i : in std_logic;
|
||||
dmem_gnt_i : in std_logic;
|
||||
dmem_outofrange_i : in std_logic;
|
||||
dmem_sbu_i : in std_logic;
|
||||
dmem_dbu_i : in std_logic;
|
||||
opcode_i : in std_logic_vector(6 downto 0);
|
||||
funct3_i : in std_logic_vector(2 downto 0);
|
||||
funct7_i : in std_logic_vector(6 downto 0);
|
||||
funct12_i : in std_logic_vector(11 downto 0);
|
||||
rstn_i : in std_logic;
|
||||
clk_i : in std_logic;
|
||||
start_i : in std_logic;
|
||||
imem_req_o : out std_logic;
|
||||
dmem_req_o : out std_logic;
|
||||
update_pc_o : out std_logic;
|
||||
trap_o : out std_logic;
|
||||
aluop_o : out std_logic_vector(ALUOP_SIZE-1 downto 0);
|
||||
alusrc_imm_o : out std_logic;
|
||||
imm_shamt_o : out std_logic;
|
||||
imm_up_o : out std_logic;
|
||||
regwr_o : out std_logic;
|
||||
inv_branch_o : out std_logic;
|
||||
branch_o : out std_logic;
|
||||
jump_o : out std_logic;
|
||||
jalr_o : out std_logic;
|
||||
ecall_o : out std_logic;
|
||||
memrd_o : out std_logic;
|
||||
memwr_o : out std_logic;
|
||||
byte_en_o : out std_logic_vector(1 downto 0);
|
||||
mem_usgn_o : out std_logic;
|
||||
load_upimm_o : out std_logic;
|
||||
auipc_o : out std_logic;
|
||||
csr_enable_o : out std_logic;
|
||||
csr_source_imm_o : out std_logic;
|
||||
csr_maskop_o : out std_logic;
|
||||
csr_clearop_o : out std_logic
|
||||
imem_gnt_i : in std_logic;
|
||||
imem_err_i : in std_logic;
|
||||
dmem_gnt_i : in std_logic;
|
||||
dmem_err_i : in std_logic;
|
||||
dmem_sbu_i : in std_logic;
|
||||
dmem_dbu_i : in std_logic;
|
||||
opcode_i : in std_logic_vector(6 downto 0);
|
||||
funct3_i : in std_logic_vector(2 downto 0);
|
||||
funct7_i : in std_logic_vector(6 downto 0);
|
||||
funct12_i : in std_logic_vector(11 downto 0);
|
||||
rstn_i : in std_logic;
|
||||
clk_i : in std_logic;
|
||||
start_i : in std_logic;
|
||||
imem_req_o : out std_logic;
|
||||
dmem_req_o : out std_logic;
|
||||
update_pc_o : out std_logic;
|
||||
trap_o : out std_logic;
|
||||
aluop_o : out std_logic_vector(ALUOP_SIZE-1 downto 0);
|
||||
alusrc_imm_o : out std_logic;
|
||||
imm_shamt_o : out std_logic;
|
||||
imm_up_o : out std_logic;
|
||||
regwr_o : out std_logic;
|
||||
inv_branch_o : out std_logic;
|
||||
branch_o : out std_logic;
|
||||
jump_o : out std_logic;
|
||||
jalr_o : out std_logic;
|
||||
ecall_o : out std_logic;
|
||||
mem_rd_o : out std_logic;
|
||||
mem_wr_o : out std_logic;
|
||||
mem_ben_o : out std_logic_vector(1 downto 0);
|
||||
mem_usgn_o : out std_logic;
|
||||
load_upimm_o : out std_logic;
|
||||
auipc_o : out std_logic;
|
||||
csr_enable_o : out std_logic;
|
||||
csr_source_imm_o : out std_logic;
|
||||
csr_maskop_o : out std_logic;
|
||||
csr_clearop_o : out std_logic
|
||||
);
|
||||
end component control;
|
||||
|
||||
component instr_fetch
|
||||
generic (
|
||||
PROGRAM_START_ADDR : std_logic_vector;
|
||||
TRAP_HANDLER_ADDR : std_logic_vector;
|
||||
PROGRAM_START_ADDR : std_logic_vector(31 downto 0);
|
||||
TRAP_HANDLER_ADDR : std_logic_vector(31 downto 0);
|
||||
HAMMING_PC : boolean
|
||||
);
|
||||
port (
|
||||
|
|
@ -208,45 +208,45 @@ package harv_pkg is
|
|||
------------- FAULT TOLERANT COMPONENTS --------------------
|
||||
component control_tmr
|
||||
port (
|
||||
imem_gnt_i : in std_logic;
|
||||
imem_err_i : in std_logic;
|
||||
dmem_gnt_i : in std_logic;
|
||||
dmem_outofrange_i : in std_logic;
|
||||
dmem_sbu_i : in std_logic;
|
||||
dmem_dbu_i : in std_logic;
|
||||
opcode_i : in std_logic_vector(6 downto 0);
|
||||
funct3_i : in std_logic_vector(2 downto 0);
|
||||
funct7_i : in std_logic_vector(6 downto 0);
|
||||
funct12_i : in std_logic_vector(11 downto 0);
|
||||
correct_error_i : in std_logic;
|
||||
rstn_i : in std_logic;
|
||||
clk_i : in std_logic;
|
||||
start_i : in std_logic;
|
||||
imem_req_o : out std_logic;
|
||||
dmem_req_o : out std_logic;
|
||||
update_pc_o : out std_logic;
|
||||
trap_o : out std_logic;
|
||||
error_o : out std_logic;
|
||||
aluop_o : out std_logic_vector(ALUOP_SIZE-1 downto 0);
|
||||
alusrc_imm_o : out std_logic;
|
||||
imm_shamt_o : out std_logic;
|
||||
imm_up_o : out std_logic;
|
||||
regwr_o : out std_logic;
|
||||
inv_branch_o : out std_logic;
|
||||
branch_o : out std_logic;
|
||||
jump_o : out std_logic;
|
||||
jalr_o : out std_logic;
|
||||
ecall_o : out std_logic;
|
||||
memrd_o : out std_logic;
|
||||
memwr_o : out std_logic;
|
||||
byte_en_o : out std_logic_vector(1 downto 0);
|
||||
mem_usgn_o : out std_logic;
|
||||
load_upimm_o : out std_logic;
|
||||
auipc_o : out std_logic;
|
||||
csr_enable_o : out std_logic;
|
||||
csr_source_imm_o : out std_logic;
|
||||
csr_maskop_o : out std_logic;
|
||||
csr_clearop_o : out std_logic
|
||||
imem_gnt_i : in std_logic;
|
||||
imem_err_i : in std_logic;
|
||||
dmem_gnt_i : in std_logic;
|
||||
dmem_err_i : in std_logic;
|
||||
dmem_sbu_i : in std_logic;
|
||||
dmem_dbu_i : in std_logic;
|
||||
opcode_i : in std_logic_vector(6 downto 0);
|
||||
funct3_i : in std_logic_vector(2 downto 0);
|
||||
funct7_i : in std_logic_vector(6 downto 0);
|
||||
funct12_i : in std_logic_vector(11 downto 0);
|
||||
correct_error_i : in std_logic;
|
||||
rstn_i : in std_logic;
|
||||
clk_i : in std_logic;
|
||||
start_i : in std_logic;
|
||||
imem_req_o : out std_logic;
|
||||
dmem_req_o : out std_logic;
|
||||
update_pc_o : out std_logic;
|
||||
trap_o : out std_logic;
|
||||
error_o : out std_logic;
|
||||
aluop_o : out std_logic_vector(ALUOP_SIZE-1 downto 0);
|
||||
alusrc_imm_o : out std_logic;
|
||||
imm_shamt_o : out std_logic;
|
||||
imm_up_o : out std_logic;
|
||||
regwr_o : out std_logic;
|
||||
inv_branch_o : out std_logic;
|
||||
branch_o : out std_logic;
|
||||
jump_o : out std_logic;
|
||||
jalr_o : out std_logic;
|
||||
ecall_o : out std_logic;
|
||||
mem_rd_o : out std_logic;
|
||||
mem_wr_o : out std_logic;
|
||||
mem_ben_o : out std_logic_vector(1 downto 0);
|
||||
mem_usgn_o : out std_logic;
|
||||
load_upimm_o : out std_logic;
|
||||
auipc_o : out std_logic;
|
||||
csr_enable_o : out std_logic;
|
||||
csr_source_imm_o : out std_logic;
|
||||
csr_maskop_o : out std_logic;
|
||||
csr_clearop_o : out std_logic
|
||||
);
|
||||
end component control_tmr;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue