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Changed the naming of instances

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This commit is contained in:
Douglas Santos 2021-10-15 11:43:12 +02:00
parent b1a6b431eb
commit 8f2b766130
8 changed files with 44 additions and 48 deletions

12
hdl/ft_components/alu_tmr.vhd
View file

@ -35,18 +35,18 @@ begin
gen_TMR : for i in 2 downto 0 generate
-- Xilinx attributes to prevent optimization of TMR
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of alu_i : label is "TRUE";
attribute DONT_TOUCH of alu_u : label is "TRUE";
-- Synplify attributes to prevent optimization of TMR
attribute syn_radhardlevel : string;
attribute syn_keep : boolean;
attribute syn_safe_case : boolean;
attribute syn_noprune : boolean;
attribute syn_radhardlevel of alu_i : label is "tmr";
attribute syn_keep of alu_i : label is TRUE;
attribute syn_safe_case of alu_i : label is TRUE;
attribute syn_noprune of alu_i : label is TRUE;
attribute syn_radhardlevel of alu_u : label is "tmr";
attribute syn_keep of alu_u : label is TRUE;
attribute syn_safe_case of alu_u : label is TRUE;
attribute syn_noprune of alu_u : label is TRUE;
begin
alu_i : alu
alu_u : alu
port map (
data1_i => data1_i,
data2_i => data2_i,

12
hdl/ft_components/control_tmr.vhd
View file

@ -157,18 +157,18 @@ begin
gen_TMR : for i in 2 downto 0 generate
-- Xilinx attributes to prevent optimization of TMR
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of control_i : label is "TRUE";
attribute DONT_TOUCH of control_u : label is "TRUE";
-- Synplify attributes to prevent optimization of TMR
attribute syn_radhardlevel : string;
attribute syn_keep : boolean;
attribute syn_safe_case : boolean;
attribute syn_noprune : boolean;
attribute syn_radhardlevel of control_i : label is "tmr";
attribute syn_keep of control_i : label is TRUE;
attribute syn_safe_case of control_i : label is TRUE;
attribute syn_noprune of control_i : label is TRUE;
attribute syn_radhardlevel of control_u : label is "tmr";
attribute syn_keep of control_u : label is TRUE;
attribute syn_safe_case of control_u : label is TRUE;
attribute syn_noprune of control_u : label is TRUE;
begin
control_i : control
control_u : control
port map (
imem_gnt_i => imem_gnt_i,
imem_err_i => imem_err_i,

4
hdl/ft_components/hamming_register.vhd
View file

@ -61,7 +61,7 @@ begin
begin
-- encode next register data
hamming_encoder_i : hamming_encoder
hamming_encoder_u : hamming_encoder
generic map (
DATA_SIZE => 32,
DETECT_DOUBLE => DETECT_DOUBLE
@ -84,7 +84,7 @@ begin
end process;
-- decode the data
hamming_decoder_i : hamming_decoder
hamming_decoder_u : hamming_decoder
generic map (
DATA_SIZE => 32,
DETECT_DOUBLE => DETECT_DOUBLE

14
hdl/harv.vhd
View file

@ -124,7 +124,7 @@ begin
clk_w <= clk_i;
instr_fetch_i : instr_fetch
instr_fetch_u : instr_fetch
generic map (
PROGRAM_START_ADDR => PROGRAM_START_ADDR,
TRAP_HANDLER_ADDR => TRAP_HANDLER_ADDR,
@ -168,7 +168,7 @@ begin
imm_i_w <= instr_w(31 downto 20);
gen_ft_control : if TMR_CONTROL generate
control_i : control_tmr
control_u : control_tmr
port map (
start_i => start_i,
imem_gnt_i => imem_gnt_i,
@ -212,7 +212,7 @@ begin
);
end generate;
gen_normal_control : if not TMR_CONTROL generate
control_i : control
control_u : control
port map (
-- processor status
start_i => start_i,
@ -268,7 +268,7 @@ begin
csr_rdata_w when ctl_csr_enable_w = '1' else
alu_data_w;
regfile_i : regfile
regfile_u : regfile
generic map (
HAMMING_ENABLE => HAMMING_REGFILE
)
@ -301,7 +301,7 @@ begin
alu_data2_w <= imm_w when ctl_alusrc_imm_w = '1' else reg_data2_w;
gen_ft_alu : if TMR_ALU generate
alu_i : alu_tmr
alu_u : alu_tmr
port map (
data1_i => alu_data1_w,
data2_i => alu_data2_w,
@ -313,7 +313,7 @@ begin
);
end generate;
gen_normal_alu : if not TMR_ALU generate
alu_i : alu
alu_u : alu
port map (
data1_i => alu_data1_w,
data2_i => alu_data2_w,
@ -328,7 +328,7 @@ begin
x"00000020" when dmem_dbu_i = '1' else -- DBU
x"00000007" when ctl_mem_wr_w = '1' else -- store address fault
x"00000005"; -- when ctl_mem_rd_w = '1' -- load address fault
csr_i : csr
csr_u : csr
generic map (
TMR_CONTROL => TMR_CONTROL,
TMR_ALU => TMR_ALU,

4
hdl/instr_fetch.vhd
View file

@ -56,7 +56,7 @@ begin
-- set PC output
pc_o <= pc_w;
register_pc_i : hamming_register
register_pc_u : hamming_register
generic map (
HAMMING_ENABLE => HAMMING_PC,
RESET_VALUE => PROGRAM_START_ADDR
@ -72,7 +72,7 @@ begin
data_o => pc_w
);
register_instr_i : hamming_register
register_instr_u : hamming_register
generic map (
HAMMING_ENABLE => HAMMING_PC,
RESET_VALUE => (31 downto 0 => '0')

6
hdl/regfile.vhd
View file

@ -84,7 +84,7 @@ begin
signal data_s1_enc_w : std_logic_vector(PARITY_BITS_QT+31 downto 0);
signal data_s2_enc_w : std_logic_vector(PARITY_BITS_QT+31 downto 0);
begin
hamming_encoder_i : hamming_encoder
hamming_encoder_u : hamming_encoder
generic map (
DATA_SIZE => 32,
DETECT_DOUBLE => DETECT_DOUBLE
@ -111,7 +111,7 @@ begin
data_s1_enc_w <= regfile_w(to_integer(unsigned(rs1_i)));
data_s2_enc_w <= regfile_w(to_integer(unsigned(rs2_i)));
hamming_decoder_data1_i : hamming_decoder
hamming_decoder_data1_u : hamming_decoder
generic map (
DATA_SIZE => 32,
DETECT_DOUBLE => DETECT_DOUBLE
@ -124,7 +124,7 @@ begin
data_o => data1_o
);
hamming_decoder_data2_i : hamming_decoder
hamming_decoder_data2_u : hamming_decoder
generic map (
DATA_SIZE => 32,
DETECT_DOUBLE => DETECT_DOUBLE

2
sim/sim_from_dump.vhd
View file

@ -87,7 +87,7 @@ begin
clk <= not clk after period/2;
start <= '1' after period * 2; -- set start signal after 2 clock cycles
harv_i : harv
harv_u : harv
generic map (
PROGRAM_START_ADDR => x"00000000",
TRAP_HANDLER_ADDR => x"00000000",

38
xilinx/sim_from_dump_behav.wcfg
View file

@ -49,54 +49,50 @@
<obj_property name="ElementShortName">imem_gnt_i</obj_property>
<obj_property name="ObjectShortName">imem_gnt_i</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/if_pc_w">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/if_pc_w">
<obj_property name="ElementShortName">if_pc_w[31:0]</obj_property>
<obj_property name="ObjectShortName">if_pc_w[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/instr_fetch_i/instr_o">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/instr_fetch_u/instr_o">
<obj_property name="ElementShortName">instr_o[31:0]</obj_property>
<obj_property name="ObjectShortName">instr_o[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/regfile_i/g_normal/regfile_w[29]">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/regfile_u/g_normal/regfile_w[29]">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[29][31:0]</obj_property>
<obj_property name="ObjectShortName">[29][31:0]</obj_property>
<obj_property name="label">reg_t4</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/regfile_i/g_normal/regfile_w[28]">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/regfile_u/g_normal/regfile_w[28]">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[28][31:0]</obj_property>
<obj_property name="ObjectShortName">[28][31:0]</obj_property>
<obj_property name="label">reg_t3</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/regfile_i/g_normal/regfile_w[7]">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/regfile_u/g_normal/regfile_w[7]">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[7][31:0]</obj_property>
<obj_property name="ObjectShortName">[7][31:0]</obj_property>
<obj_property name="label">reg_t2</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/regfile_i/g_normal/regfile_w[6]">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/regfile_u/g_normal/regfile_w[6]">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[6][31:0]</obj_property>
<obj_property name="ObjectShortName">[6][31:0]</obj_property>
<obj_property name="label">reg_t1</obj_property>
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/regfile_i/g_normal/regfile_w[5]">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/regfile_u/g_normal/regfile_w[5]">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">[5][31:0]</obj_property>
<obj_property name="ObjectShortName">[5][31:0]</obj_property>
<obj_property name="label">reg_t0</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/regfile_i/g_normal/regfile_w[10]">
<obj_property name="ElementShortName">[10][31:0]</obj_property>
<obj_property name="ObjectShortName">[10][31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/regfile_i/g_normal/regfile_w">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/regfile_u/g_normal/regfile_w">
<obj_property name="ElementShortName">regfile_w[31:0][31:0]</obj_property>
<obj_property name="ObjectShortName">regfile_w[31:0][31:0]</obj_property>
</wvobject>
@ -104,39 +100,39 @@
<obj_property name="label">CORE</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/gen_normal_control/control_i/proc_status_r">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/gen_normal_control/control_u/proc_status_r">
<obj_property name="ElementShortName">proc_status_r[2:0]</obj_property>
<obj_property name="ObjectShortName">proc_status_r[2:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/regfile_i/data_i">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/regfile_u/data_i">
<obj_property name="ElementShortName">data_i[31:0]</obj_property>
<obj_property name="ObjectShortName">data_i[31:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/sim_from_dump/harv_i/regfile_i/wren_i">
<wvobject type="logic" fp_name="/sim_from_dump/harv_u/regfile_u/wren_i">
<obj_property name="ElementShortName">wren_i</obj_property>
<obj_property name="ObjectShortName">wren_i</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/sim_from_dump/harv_i/instr_fetch_i/jump_i">
<wvobject type="logic" fp_name="/sim_from_dump/harv_u/instr_fetch_u/jump_i">
<obj_property name="ElementShortName">jump_i</obj_property>
<obj_property name="ObjectShortName">jump_i</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/instr_fetch_i/jump_imm_i">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/instr_fetch_u/jump_imm_i">
<obj_property name="ElementShortName">jump_imm_i[31:0]</obj_property>
<obj_property name="ObjectShortName">jump_imm_i[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/imm_i_w">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/imm_i_w">
<obj_property name="ElementShortName">imm_i_w[11:0]</obj_property>
<obj_property name="ObjectShortName">imm_i_w[11:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/imm_w">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/imm_w">
<obj_property name="ElementShortName">imm_w[31:0]</obj_property>
<obj_property name="ObjectShortName">imm_w[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/ctl_aluop_w">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/ctl_aluop_w">
<obj_property name="ElementShortName">ctl_aluop_w[3:0]</obj_property>
<obj_property name="ObjectShortName">ctl_aluop_w[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/sim_from_dump/harv_i/alu_data_w">
<wvobject type="array" fp_name="/sim_from_dump/harv_u/alu_data_w">
<obj_property name="ElementShortName">alu_data_w[31:0]</obj_property>
<obj_property name="ObjectShortName">alu_data_w[31:0]</obj_property>
</wvobject>