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59 lines
2.3 KiB
VHDL
59 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.harv_pkg.all;
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entity alu is
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port (
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-- input ports
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data1_i : in std_logic_vector(31 downto 0);
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data2_i : in std_logic_vector(31 downto 0);
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operation_i : in std_logic_vector(ALUOP_SIZE-1 downto 0);
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-- output ports
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zero_o : out std_logic;
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data_o : out std_logic_vector(31 downto 0)
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);
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end entity;
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architecture arch of alu is
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signal add_sub_data2_w : signed(31 downto 0);
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signal add_sub_w : std_logic_vector(31 downto 0);
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signal and_w : std_logic_vector(31 downto 0);
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signal or_w : std_logic_vector(31 downto 0);
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signal xor_w : std_logic_vector(31 downto 0);
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signal sll_w : std_logic_vector(31 downto 0);
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signal srl_w : std_logic_vector(31 downto 0);
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signal sra_w : std_logic_vector(31 downto 0);
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signal slt_w : std_logic_vector(31 downto 0);
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signal sltu_w : std_logic_vector(31 downto 0);
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signal result_w : std_logic_vector(31 downto 0);
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begin
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add_sub_data2_w <= signed(data2_i) when operation_i = ALU_ADD_OP else -signed(data2_i);
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add_sub_w <= std_logic_vector(signed(data1_i) + add_sub_data2_w);
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and_w <= data1_i and data2_i;
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or_w <= data1_i or data2_i;
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xor_w <= data1_i xor data2_i;
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sll_w <= std_logic_vector(shift_left(unsigned(data1_i), to_integer(unsigned(data2_i))));
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srl_w <= std_logic_vector(shift_right(unsigned(data1_i), to_integer(unsigned(data2_i))));
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sra_w <= std_logic_vector(shift_right(signed(data1_i), to_integer(unsigned(data2_i))));
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slt_w <= (0 => '1', others => '0') when signed(data1_i) < signed(data2_i) else (others => '0');
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sltu_w <= (0 => '1', others => '0') when unsigned(data1_i) < unsigned(data2_i) else (others => '0');
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with operation_i select result_w <=
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add_sub_w when ALU_ADD_OP,
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add_sub_w when ALU_SUB_OP,
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sll_w when ALU_SLL_OP,
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slt_w when ALU_SLT_OP,
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sltu_w when ALU_SLTU_OP,
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xor_w when ALU_XOR_OP,
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srl_w when ALU_SRL_OP,
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sra_w when ALU_SRA_OP,
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or_w when ALU_OR_OP,
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and_w when ALU_AND_OP,
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(others => '0') when others;
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data_o <= result_w;
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zero_o <= '1' when result_w = (31 downto 0 => '0') else '0';
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end architecture;
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