Fix SRAM initialisation for fpga/artya example

This now gets passed to the underlying primitive as a
parameter (instead of a define).

examples/fpga/artya7/rtl/top_artya7.sv

@@ -8,9 +8,10 @@ module top_artya7 (
     output [3:0]        LED
 );
 
-  parameter int          MEM_SIZE  = 64 * 1024; // 64 kB
-  parameter logic [31:0] MEM_START = 32'h00000000;
-  parameter logic [31:0] MEM_MASK  = MEM_SIZE-1;
+  parameter int          MEM_SIZE     = 64 * 1024; // 64 kB
+  parameter logic [31:0] MEM_START    = 32'h00000000;
+  parameter logic [31:0] MEM_MASK     = MEM_SIZE-1;
+  parameter              SRAMInitFile = "";
 
   logic clk_sys, rst_sys_n;
 
@@ -104,7 +105,8 @@ module top_artya7 (
 
   // SRAM block for instruction and data storage
   ram_1p #(
-    .Depth(MEM_SIZE / 4)
+    .Depth(MEM_SIZE / 4),
+    .MemInitFile(SRAMInitFile)
   ) u_ram (
     .clk_i     ( clk_sys        ),
     .rst_ni    ( rst_sys_n      ),

examples/fpga/artya7/top_artya7.core

@@ -21,15 +21,15 @@ filesets:
 parameters:
   # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
   # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
-  # --SRAM_INIT_FILE=$PWD/sw/led/led.vmem
+  # --SRAMInitFile=$PWD/sw/led/led.vmem
   # XXX: The VMEM file should be added to the sources of the Vivado project to
   # make the Vivado dependency tracking work. However this requires changes to
   # fusesoc first.
-  SRAM_INIT_FILE:
+  SRAMInitFile:
     datatype: str
     description: SRAM initialization file in vmem hex format
     default: "../../../../../examples/sw/led/led.vmem"
-    paramtype: vlogdefine
+    paramtype: vlogparam
 
   FPGA_XILINX:
     datatype: str
@@ -45,7 +45,7 @@ targets:
       - files_constraints
     toplevel: top_artya7
     parameters:
-      - SRAM_INIT_FILE
+      - SRAMInitFile
       - FPGA_XILINX
     tools:
       vivado: