mirror of
https://github.com/lowRISC/ibex.git
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Create a clean code generation script for littleRISCV called ri5cly-manage.py
This commit is contained in:
Markus Wegmann
parent
7c99161125
commit
00a2c3a8fb
7 changed files with 222 additions and 15 deletions
2
.gitignore
vendored
2
.gitignore
vendored
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@ -1,3 +1 @@
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*.swp
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@ -602,7 +602,6 @@ module riscv_decoder
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{6'b00_0000, 3'b101}: alu_operator_o = ALU_SRL; // Shift Right Logical
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{6'b10_0000, 3'b101}: alu_operator_o = ALU_SRA; // Shift Right Arithmetic
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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// supported RV32M instructions
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@ -1096,6 +1095,9 @@ module riscv_decoder
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end
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// CONFIG_REGION: HWL_SUPPORT
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`ifdef HWL_SUPPORT
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///////////////////////////////////////////////
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// _ ___ ___ ___ ___ ____ //
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// | | | \ \ / / | / _ \ / _ \| _ \ //
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@ -1105,8 +1107,7 @@ module riscv_decoder
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// //
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///////////////////////////////////////////////
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// CONFIG_REGION: HWL_SUPPORT
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`ifdef HWL_SUPPORT
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OPCODE_HWLOOP: begin
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hwloop_target_mux_sel_o = 1'b0;
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@ -231,6 +231,9 @@ module riscv_ex_stage
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`endif // SIMPLE_ALU
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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////////////////////////////////////////////////////////////////
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// __ __ _ _ _ _____ ___ ____ _ ___ _____ ____ //
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// | \/ | | | | | |_ _|_ _| _ \| | |_ _| ____| _ \ //
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@ -240,8 +243,7 @@ module riscv_ex_stage
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// //
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////////////////////////////////////////////////////////////////
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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riscv_mult mult_i
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(
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.clk ( clk ),
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13
id_stage.sv
13
id_stage.sv
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@ -82,7 +82,6 @@ module riscv_id_stage
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input logic [31:0] instr_rdata_i, // comes from pipeline of IF stage
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output logic instr_req_o,
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// Jumps and branches
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output logic branch_in_ex_o,
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input logic branch_decision_i,
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@ -126,7 +125,7 @@ module riscv_id_stage
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output logic [ 4:0] bmask_b_ex_o,
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`endif // BIT_SUPPORT
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// CONFIG_REGION: VEC_SUPPORT
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// CONFIG_REGION: VEC_SUPPORT
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`ifdef VEC_SUPPORT
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output logic [ 1:0] imm_vec_ext_ex_o,
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output logic [ 1:0] alu_vec_mode_ex_o,
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@ -141,7 +140,6 @@ module riscv_id_stage
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// ALU
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output logic [ALU_OP_WIDTH-1:0] alu_operator_ex_o,
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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// MUL
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@ -583,6 +581,10 @@ module riscv_id_stage
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assign mult_en = mult_int_en | mult_dot_en;
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`endif // MUL_SUPPORT
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// CONFIG_REGION: HWL_SUPPORT
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`ifdef HWL_SUPPORT
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///////////////////////////////////////////////
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// _ ___ ___ ___ ___ ____ //
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// | | | \ \ / / | / _ \ / _ \| _ \ //
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@ -592,8 +594,7 @@ module riscv_id_stage
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// //
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///////////////////////////////////////////////
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// CONFIG_REGION: HWL_SUPPORT
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`ifdef HWL_SUPPORT
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// hwloop register id
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assign hwloop_regid_int = instr[7]; // rd contains hwloop register id
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@ -914,7 +915,7 @@ module riscv_id_stage
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default: mult_imm_id = '0;
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endcase
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end
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`endif // MUL_SUPPORT
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`endif // MUL_SUPPORT
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/////////////////////////////////////////////////////////
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// ____ _____ ____ ___ ____ _____ _____ ____ ____ //
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@ -32,7 +32,15 @@
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`endif
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// littleRISCV configuration. Decomment to enable.
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// littleRISCV configuration.
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// Decomment to enable.
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// The format should be strictly followed so the ri5cly-manage tool can parse the configuration
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// A CONFIG section declares a config definition, a CONFIG_REGION enables the tool to remove disabled code
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// for export. See the ri5cly-manage.py tool help and source code in the /scripts folder for more information.
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// CONFIG: MUL_SUPPORT
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// will enable RISCV32M support for multiplication, division, MAC operations. Uses a lot of multiplications
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@ -73,6 +81,7 @@
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// Dependent definitions
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// CONFIG: THREE_PORT_REG_FILE
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// enables 3r2w reg file (rather than 2r1w)
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//`define THREE_PORT_REG_FILE
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@ -96,7 +105,6 @@
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// will reduce the register file to 16 words
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`define RV32E
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`endif
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`endif
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`endif
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2
scripts/.gitignore
vendored
Normal file
2
scripts/.gitignore
vendored
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@ -0,0 +1,2 @@
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build/
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.idea/
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195
scripts/ri5cly-manage.py
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195
scripts/ri5cly-manage.py
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@ -0,0 +1,195 @@
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#!/bin/python3
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import os
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import shutil
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import argparse
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import re
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def main():
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littleRISCV_path = os.path.abspath(os.path.dirname(os.path.realpath(__file__)) + "/..") # Path to littleRISCV folder
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print(littleRISCV_path)
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parser = argparse.ArgumentParser(description="Can overwrite config and export clean version of littleRISCV")
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parser.add_argument('-i', dest="new_riscv_config", metavar='.../new_riscv_config.sv',
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help='path to a new config file to overwrite littleRISCV config')
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parser.add_argument('-o', dest='build_folder_path', metavar='.../build_folder_path',
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help='path to a folder to export clean version of littleRISCV without preprocessor switches')
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parser.add_argument('-z', dest='zip', action='store_true',
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help='zip the export into a tar.gz')
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args = parser.parse_args()
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action_taken = False
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if args.new_riscv_config is not None:
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overwriteConfig(args["new_riscv_config.sv"], littleRISCV_path)
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action_taken = True
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if args.build_folder_path is not None:
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exportCleanVersion(args.build_folder_path, littleRISCV_path, zip=args.zip)
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action_taken = True
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if action_taken == False:
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print("No action taken. Please see the help below for more information:")
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parser.print_help()
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def overwriteConfig(new_config_path, littleRISCV_path):
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print("Overwriting current config (include/riscv_config.sv) with new one.")
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shutil.move(os.path.abspath(littleRISCV_path + "/include/riscv_config.sv"), os.path.abspath(littleRISCV_path + "/include/riscv_config.sv.bak")) # Backup
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shutil.copy(os.path.abspath(new_config_path), os.path.abspath(littleRISCV_path + "/include/riscv_config.sv")) # Copy new config to littleRISCV
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def parseConfig(littleRISCV_path):
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print("Trying to parse configuration.")
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definitions = []
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config = os.path.abspath(littleRISCV_path + "/include/riscv_config.sv")
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with open(config, encoding="utf8") as f:
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nesting_counter = 0 # If we enter a not-enabled section, keep track when we leave the section again
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content = f.readlines()
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while len(content) > 0:
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line = content.pop(0)
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config_pattern = re.compile("^//.*CONFIG:\s(\w*)$") # Test for config declaration
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m = config_pattern.match(line)
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if m is not None and nesting_counter == 0:
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content.pop(0) # Pop description
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line = content.pop(0)
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config_value_pattern = re.compile("^`define\s(\w*)$") # Check if config enabled and extract name
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m = config_value_pattern.match(line)
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if m is not None:
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definitions.append(m.group(1))
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else:
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ifdef_pattern = re.compile("^`ifdef\s(\w*)$") # Check if we have a dependant config
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m = ifdef_pattern.match(line)
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if m is not None:
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if m.group(1) in definitions:
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pass
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else:
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nesting_counter += 1
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ifndef_pattern = re.compile("^`ifndef\s(\w*)$") # Check if we have a dependant config
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m = ifndef_pattern.match(line)
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if m is not None:
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if not (m.group(1) in definitions):
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pass
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else:
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nesting_counter += 1
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endif_pattern = re.compile("^`endif.*$") # Check if we ended a block
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m = endif_pattern.match(line)
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if m is not None:
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nesting_counter -= 1
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if nesting_counter < 0:
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nesting_counter = 0
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print("Enabled CONFIG definitions: {}".format(definitions))
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return definitions
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def processSystemVerilog(filename, folderpath, definitions):
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print("Processing: {}".format(filename))
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content = []
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new_content = []
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with open(os.path.abspath(folderpath+"/"+filename), encoding="utf8") as f:
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content = f.readlines()
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nesting_counter = 0 # If we enter a not-enabled section, keep track when we leave the section again
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is_else_true = False # at first occurence of missing declarations
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while len(content) > 0:
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is_codeline = True
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line = content.pop(0)
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config_pattern = re.compile("^\s*//.*CONFIG_REGION:\s(\w*)$") # Test for config region declaration
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m = config_pattern.match(line)
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if m is not None:
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is_codeline = False
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line = content.pop(0)
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ifdef_pattern = re.compile("^\s*`ifdef\s(\w*)$") # Check if we have an ifdef
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m = ifdef_pattern.match(line)
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if m is not None:
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if m.group(1) in definitions:
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if nesting_counter == 0:
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is_else_true = False
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else:
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nesting_counter += 1
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else:
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if nesting_counter == 0:
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is_else_true = True
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nesting_counter += 1
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ifndef_pattern = re.compile("^\s*`ifndef\s(\w*)$") # Check if we have an ifndef
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m = ifndef_pattern.match(line)
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if m is not None:
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if not (m.group(1) in definitions):
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if nesting_counter == 0:
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is_else_true = False
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else:
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nesting_counter += 1
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else:
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if nesting_counter == 0:
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is_else_true = True
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nesting_counter += 1
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else_pattern = re.compile("^\s*`else.*$") # Check if we have an else
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m = else_pattern.match(line)
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if m is not None:
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is_codeline = False
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if nesting_counter == 1 and is_else_true:
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nesting_counter -= 1
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if (not is_else_true) and nesting_counter == 0:
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nesting_counter += 1
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endif_pattern = re.compile("^\s*`endif.*$") # Check if we have an endif
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m = endif_pattern.match(line)
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if m is not None:
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is_codeline = False
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nesting_counter -= 1
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if nesting_counter < 0:
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nesting_counter = 0
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if is_codeline and nesting_counter == 0:
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new_content.append(line)
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os.remove(os.path.abspath(folderpath+"/"+filename))
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with open(os.path.abspath(folderpath+"/"+filename), 'w', encoding="utf8") as f:
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f.writelines(new_content)
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def exportCleanVersion(build_path, littleRISCV_path, zip=False):
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print("Exporting clean version of littleRISCV without preprocessor switches to defined output folder.")
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definitions = parseConfig(littleRISCV_path)
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shutil.rmtree(os.path.abspath(build_path), ignore_errors=True)
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shutil.copytree(os.path.abspath(littleRISCV_path), os.path.abspath(build_path), ignore=shutil.ignore_patterns("*.git", "scripts", "docs"))
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for filename in os.listdir(os.path.abspath(build_path)):
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sv_p = re.compile("^.*\.sv")
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m = sv_p.match(filename)
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if m is not None:
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processSystemVerilog(filename, build_path, definitions)
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with open(os.path.abspath(build_path+"/THIS_CORE_IS_AUTOMATICALLY_GENERATATED!!!.txt"), 'w', encoding="utf8") as f:
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f.write("This core export was automatically generated by ri5cly-manage.py\n\n")
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f.write("Following settings were enabled: {}".format(definitions))
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if __name__ == "__main__":
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main()
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