mirror of
https://github.com/lowRISC/ibex.git
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Tracer rewrite
Instantiate tracer module in a separate core file and use only RVFI signals.
This commit is contained in:
Tobias Wölfel
Philipp Wagner
parent
1e2d5b7eda
commit
014c753dde
8 changed files with 237 additions and 134 deletions
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@ -16,6 +16,7 @@ Ibex User Manual
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exception_interrupts
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interrupts
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debug
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tracer
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rvfi
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@ -48,6 +48,7 @@ The control and status registers are explained in :ref:`cs-registers`.
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:ref:`performance-counters` gives an overview of the performance monitors and event counters available in Ibex.
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:ref:`exceptions-interrupts` deals with the infrastructure for handling exceptions and interrupts,
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:ref:`debug-support` gives a brief overview on the debug infrastructure.
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:ref:`tracer` gives a brief overview of the tracer module.
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For information regarding formal verification support, check out :ref:`rvfi`.
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11
doc/tracer.rst
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11
doc/tracer.rst
Normal file
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@ -0,0 +1,11 @@
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.. _tracer:
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Tracer
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======
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The module ``ibex_tracer`` can be used to create a log of the executed instructions.
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It is used by ``ibex_core_tracer`` which forwards the signals added by :ref:`rvfi` as an input for the tracer.
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.. note::
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``ibex_tracer`` is not compatible with Verilator.
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@ -11,9 +11,18 @@ filesets:
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files:
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- rtl/ibex_tracer_defines.sv
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- rtl/ibex_tracer.sv
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- rtl/ibex_core_tracer.sv
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file_type: systemVerilogSource
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parameters:
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RVFI:
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datatype: bool
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paramtype: vlogdefine
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description: Enable RVFI signals for tracing
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targets:
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default:
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filesets:
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- files_rtl
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parameters:
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- RVFI=true
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@ -747,56 +747,4 @@ module ibex_core #(
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assign rvfi_changed_pc = rvfi_pc_id_q != pc_id;
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`endif
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`ifndef VERILATOR
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`ifdef TRACE_EXECUTION
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ibex_tracer ibex_tracer_i (
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.clk_i ( clk_i ), // always-on clk for tracer
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.rst_ni ( rst_ni ),
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.fetch_enable_i ( fetch_enable_i ),
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.core_id_i ( core_id_i ),
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.cluster_id_i ( cluster_id_i ),
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.pc_i ( id_stage_i.pc_id_i ),
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.instr_i ( id_stage_i.instr_rdata_i ),
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.compressed_i ( id_stage_i.instr_is_compressed_i ),
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.id_valid_i ( id_stage_i.id_valid_o ),
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.is_decoding_i ( id_stage_i.is_decoding_o ),
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.is_branch_i ( id_stage_i.branch_in_id ),
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.branch_taken_i ( id_stage_i.branch_set_q ),
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.pipe_flush_i ( id_stage_i.controller_i.pipe_flush_i ),
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.mret_insn_i ( id_stage_i.controller_i.mret_insn_i ),
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.dret_insn_i ( id_stage_i.controller_i.dret_insn_i ),
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.ecall_insn_i ( id_stage_i.controller_i.ecall_insn_i ),
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.ebrk_insn_i ( id_stage_i.controller_i.ebrk_insn_i ),
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.csr_status_i ( id_stage_i.controller_i.csr_status_i ),
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.rs1_value_i ( id_stage_i.operand_a_fw_id ),
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.rs2_value_i ( id_stage_i.operand_b_fw_id ),
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.lsu_value_i ( data_wdata_ex ),
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.ex_reg_addr_i ( id_stage_i.regfile_waddr ),
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.ex_reg_we_i ( id_stage_i.regfile_we ),
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.ex_reg_wdata_i ( id_stage_i.regfile_wdata ),
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.lsu_data_valid_i ( lsu_data_valid ),
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.ex_data_addr_i ( data_addr_o ),
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.ex_data_req_i ( data_req_o ),
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.ex_data_gnt_i ( data_gnt_i ),
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.ex_data_we_i ( data_we_o ),
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.ex_data_wdata_i ( data_wdata_o ),
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.lsu_reg_wdata_i ( regfile_wdata_lsu ),
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.imm_i_type_i ( id_stage_i.imm_i_type ),
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.imm_s_type_i ( id_stage_i.imm_s_type ),
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.imm_b_type_i ( id_stage_i.imm_b_type ),
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.imm_u_type_i ( id_stage_i.imm_u_type ),
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.imm_j_type_i ( id_stage_i.imm_j_type ),
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.zimm_rs1_type_i ( id_stage_i.zimm_rs1_type )
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);
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`endif
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`endif
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endmodule
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180
rtl/ibex_core_tracer.sv
Normal file
180
rtl/ibex_core_tracer.sv
Normal file
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@ -0,0 +1,180 @@
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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// ibex_tracer relies on the signals from the RISC-V Formal Interface
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`define RVFI
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/**
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* Top level module of the ibex RISC-V core with tracing enabled
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*/
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module ibex_core_tracer #(
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parameter int unsigned MHPMCounterNum = 8,
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parameter int unsigned MHPMCounterWidth = 40,
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parameter bit RV32E = 0,
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parameter bit RV32M = 1,
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parameter int unsigned DmHaltAddr = 32'h1A110800,
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parameter int unsigned DmExceptionAddr = 32'h1A110808
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) (
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// Clock and Reset
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input logic clk_i,
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input logic rst_ni,
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input logic test_en_i, // enable all clock gates for testing
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// Core ID, Cluster ID and boot address are considered more or less static
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input logic [ 3:0] core_id_i,
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input logic [ 5:0] cluster_id_i,
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input logic [31:0] boot_addr_i,
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// Instruction memory interface
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output logic instr_req_o,
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input logic instr_gnt_i,
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input logic instr_rvalid_i,
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output logic [31:0] instr_addr_o,
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input logic [31:0] instr_rdata_i,
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// Data memory interface
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output logic data_req_o,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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output logic data_we_o,
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output logic [3:0] data_be_o,
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output logic [31:0] data_addr_o,
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output logic [31:0] data_wdata_o,
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input logic [31:0] data_rdata_i,
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input logic data_err_i,
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// Interrupt inputs
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input logic irq_i, // level sensitive IR lines
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input logic [4:0] irq_id_i,
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output logic irq_ack_o, // irq ack
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output logic [4:0] irq_id_o,
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// Debug Interface
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input logic debug_req_i,
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// RISC-V Formal Interface
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// Does not comply with the coding standards of _i/_o suffixes, but follows
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// the convention of RISC-V Formal Interface Specification.
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`ifdef RVFI
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output logic rvfi_valid,
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output logic [63:0] rvfi_order,
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output logic [31:0] rvfi_insn,
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output logic rvfi_trap,
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output logic rvfi_halt,
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output logic rvfi_intr,
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output logic [ 1:0] rvfi_mode,
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output logic [ 4:0] rvfi_rs1_addr,
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output logic [ 4:0] rvfi_rs2_addr,
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output logic [31:0] rvfi_rs1_rdata,
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output logic [31:0] rvfi_rs2_rdata,
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output logic [ 4:0] rvfi_rd_addr,
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output logic [31:0] rvfi_rd_wdata,
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output logic [31:0] rvfi_pc_rdata,
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output logic [31:0] rvfi_pc_wdata,
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output logic [31:0] rvfi_mem_addr,
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output logic [ 3:0] rvfi_mem_rmask,
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output logic [ 3:0] rvfi_mem_wmask,
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output logic [31:0] rvfi_mem_rdata,
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output logic [31:0] rvfi_mem_wdata,
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`endif
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// CPU Control Signals
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input logic fetch_enable_i
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);
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import ibex_defines::*;
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ibex_core #(
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.MHPMCounterNum(MHPMCounterNum),
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.MHPMCounterWidth(MHPMCounterWidth),
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.RV32E(RV32E),
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.RV32M(RV32M),
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.DmHaltAddr(DmHaltAddr),
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.DmExceptionAddr(DmExceptionAddr)
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) u_ibex_core (
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.clk_i,
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.rst_ni,
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.test_en_i,
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.core_id_i,
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.cluster_id_i,
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.boot_addr_i,
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.instr_req_o,
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.instr_gnt_i,
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.instr_rvalid_i,
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.instr_addr_o,
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.instr_rdata_i,
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.data_req_o,
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.data_gnt_i,
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.data_rvalid_i,
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.data_we_o,
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.data_be_o,
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.data_addr_o,
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.data_wdata_o,
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.data_rdata_i,
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.data_err_i,
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.irq_i,
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.irq_id_i,
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.irq_ack_o,
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.irq_id_o,
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.debug_req_i,
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`ifdef RVFI
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.rvfi_valid,
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.rvfi_order,
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.rvfi_insn,
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.rvfi_trap,
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.rvfi_halt,
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.rvfi_intr,
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.rvfi_mode,
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.rvfi_rs1_addr,
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.rvfi_rs2_addr,
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.rvfi_rs1_rdata,
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.rvfi_rs2_rdata,
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.rvfi_rd_addr,
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.rvfi_rd_wdata,
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.rvfi_pc_rdata,
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.rvfi_pc_wdata,
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.rvfi_mem_addr,
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.rvfi_mem_rmask,
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.rvfi_mem_wmask,
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.rvfi_mem_rdata,
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.rvfi_mem_wdata,
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`endif
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.fetch_enable_i
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);
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`ifndef VERILATOR
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ibex_tracer ibex_tracer_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.fetch_enable_i ( fetch_enable_i ),
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.core_id_i ( core_id_i ),
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.cluster_id_i ( cluster_id_i ),
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.valid_i ( rvfi_valid ),
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.pc_i ( rvfi_pc_rdata ),
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.instr_i ( rvfi_insn ),
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.rs1_value_i ( rvfi_rs1_rdata ),
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.rs2_value_i ( rvfi_rs2_rdata ),
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.ex_reg_addr_i ( rvfi_rd_addr ),
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.ex_reg_wdata_i ( rvfi_rd_wdata ),
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.ex_data_addr_i ( rvfi_mem_addr ),
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.ex_data_wdata_i ( rvfi_mem_wdata ),
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.ex_data_rdata_i ( rvfi_mem_rdata )
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);
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`endif // VERILATOR
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endmodule
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@ -228,10 +228,6 @@ module ibex_id_stage #(
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// CSR control
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logic csr_status;
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// For tracer
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logic [31:0] operand_a_fw_id, unused_operand_a_fw_id;
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logic [31:0] operand_b_fw_id, unused_operand_b_fw_id;
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logic [31:0] alu_operand_a;
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logic [31:0] alu_operand_b;
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@ -286,13 +282,6 @@ module ibex_id_stage #(
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// ALU MUX for Operand B
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assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM) ? imm_b : regfile_rdata_b;
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// Signals used by tracer
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assign operand_a_fw_id = lsu_addr_incr_req_i ? lsu_addr_last_i : regfile_rdata_a;
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assign operand_b_fw_id = regfile_rdata_b;
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assign unused_operand_a_fw_id = operand_a_fw_id;
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assign unused_operand_b_fw_id = operand_b_fw_id;
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///////////////////////
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// Register File MUX //
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///////////////////////
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@ -42,41 +42,16 @@ module ibex_tracer #(
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input logic [3:0] core_id_i,
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input logic [5:0] cluster_id_i,
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input logic valid_i,
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input logic [31:0] pc_i,
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input logic [31:0] instr_i,
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input logic compressed_i,
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input logic id_valid_i,
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input logic is_decoding_i,
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input logic is_branch_i,
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input logic branch_taken_i,
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input logic pipe_flush_i,
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input logic mret_insn_i,
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input logic dret_insn_i,
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input logic ecall_insn_i,
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input logic ebrk_insn_i,
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input logic csr_status_i,
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input logic [31:0] rs1_value_i,
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input logic [31:0] rs2_value_i,
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input logic [31:0] lsu_value_i,
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input logic [(RegAddrWidth-1):0] ex_reg_addr_i,
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input logic ex_reg_we_i,
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input logic [31:0] ex_reg_wdata_i,
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input logic lsu_data_valid_i,
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input logic ex_data_req_i,
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input logic ex_data_gnt_i,
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input logic ex_data_we_i,
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input logic [31:0] ex_data_addr_i,
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input logic [31:0] ex_data_wdata_i,
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input logic [31:0] lsu_reg_wdata_i,
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input logic [31:0] imm_i_type_i,
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input logic [31:0] imm_s_type_i,
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input logic [31:0] imm_b_type_i,
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input logic [31:0] imm_u_type_i,
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input logic [31:0] imm_j_type_i,
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input logic [31:0] zimm_rs1_type_i
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input logic [31:0] ex_data_rdata_i
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);
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integer f;
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@ -135,20 +110,26 @@ module ibex_tracer #(
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foreach(regs_write[i]) begin
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if (regs_write[i].addr != 0) begin
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$fwrite(f, " %s=%08x", regAddrToStr(regs_write[i].addr), regs_write[i].value);
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$fwrite(f, " %s=0x%08x", regAddrToStr(regs_write[i].addr), regs_write[i].value);
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end
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end
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foreach(regs_read[i]) begin
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if (regs_read[i].addr != 0) begin
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$fwrite(f, " %s:%08x", regAddrToStr(regs_read[i].addr), regs_read[i].value);
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$fwrite(f, " %s:0x%08x", regAddrToStr(regs_read[i].addr), regs_read[i].value);
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end
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end
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if (mem_access.size() > 0) begin
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mem_acc = mem_access.pop_front();
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$fwrite(f, " PA:%08x", mem_acc.addr);
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$fwrite(f, " PA:0x%08x", mem_acc.addr);
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if (mem_acc.we == 1'b1) begin
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$fwrite(f, " store:0x%08x", mem_acc.wdata);
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end else begin
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$fwrite(f, " load:0x%08x", mem_acc.rdata);
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end
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end
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$fwrite(f, "\n");
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@ -174,7 +155,7 @@ module ibex_tracer #(
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begin
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regs_read.push_back('{rs1, rs1_value_i});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $signed(imm_i_type_i));
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str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $signed({{20 {instr[31]}}, instr[31:20]}));
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end
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endfunction // printIInstr
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@ -182,21 +163,21 @@ module ibex_tracer #(
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begin
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regs_read.push_back('{rs1, rs1_value_i});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, 0x%0x", mnemonic, rd, rs1, imm_i_type_i);
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str = $sformatf("%-16s x%0d, x%0d, 0x%0x", mnemonic, rd, rs1, {{20 {instr[31]}}, instr[31:20]});
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end
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endfunction // printIuInstr
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function void printUInstr(input string mnemonic);
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begin
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {imm_u_type_i[31:12], 12'h000});
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str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {instr[31:12], 12'h000});
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end
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endfunction // printUInstr
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function void printUJInstr(input string mnemonic);
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begin
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, %0d", mnemonic, rd, $signed(imm_j_type_i));
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str = $sformatf("%-16s x%0d, %0d", mnemonic, rd, $signed({ {12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 }));
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end
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||||
endfunction // printUJInstr
|
||||
|
||||
|
|
@ -204,7 +185,7 @@ module ibex_tracer #(
|
|||
begin
|
||||
regs_read.push_back('{rs1, rs1_value_i});
|
||||
regs_read.push_back('{rs2, rs2_value_i});
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||||
str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rs1, rs2, $signed(imm_b_type_i));
|
||||
str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rs1, rs2, $signed({ {19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 }));
|
||||
end
|
||||
endfunction // printSBInstr
|
||||
|
||||
|
|
@ -219,14 +200,15 @@ module ibex_tracer #(
|
|||
regs_read.push_back('{rs1, rs1_value_i});
|
||||
str = $sformatf("%-16s x%0d, x%0d, 0x%h", mnemonic, rd, rs1, csr);
|
||||
end else begin
|
||||
str = $sformatf("%-16s x%0d, 0x%h, 0x%h", mnemonic, rd, zimm_rs1_type_i, csr);
|
||||
str = $sformatf("%-16s x%0d, 0x%h, 0x%h", mnemonic, rd, { 27'b0, instr[`REG_S1] }, csr);
|
||||
end
|
||||
end
|
||||
endfunction // printCSRInstr
|
||||
|
||||
function void printLoadInstr();
|
||||
string mnemonic;
|
||||
string mnemonic;
|
||||
logic [2:0] size;
|
||||
mem_acc_t mem_acc;
|
||||
begin
|
||||
// detect reg-reg load and find size
|
||||
size = instr_i[14:12];
|
||||
|
|
@ -257,15 +239,20 @@ module ibex_tracer #(
|
|||
if (instr_i[14:12] != 3'b111) begin
|
||||
// regular load
|
||||
regs_read.push_back('{rs1, rs1_value_i});
|
||||
str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, $signed(imm_i_type_i), rs1);
|
||||
str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, $signed({{20 {instr[31]}}, instr[31:20]}), rs1);
|
||||
end else begin
|
||||
printMnemonic("INVALID");
|
||||
end
|
||||
|
||||
mem_acc.addr = ex_data_addr_i;
|
||||
mem_acc.rdata = ex_data_rdata_i;
|
||||
mem_access.push_back(mem_acc);
|
||||
end
|
||||
endfunction
|
||||
|
||||
function void printStoreInstr();
|
||||
string mnemonic;
|
||||
string mnemonic;
|
||||
mem_acc_t mem_acc;
|
||||
begin
|
||||
|
||||
unique case (instr_i[13:12])
|
||||
|
|
@ -286,10 +273,15 @@ module ibex_tracer #(
|
|||
// regular store
|
||||
regs_read.push_back('{rs2, rs2_value_i});
|
||||
regs_read.push_back('{rs1, rs1_value_i});
|
||||
str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed(imm_s_type_i), rs1);
|
||||
str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed({ {20 {instr[31]}}, instr[31:25], instr[11:7] }), rs1);
|
||||
end else begin
|
||||
printMnemonic("INVALID");
|
||||
end
|
||||
|
||||
mem_acc.addr = ex_data_addr_i;
|
||||
mem_acc.we = 1'b1;
|
||||
mem_acc.wdata = ex_data_wdata_i;
|
||||
mem_access.push_back(mem_acc);
|
||||
end
|
||||
endfunction // printSInstr
|
||||
|
||||
|
|
@ -327,12 +319,11 @@ module ibex_tracer #(
|
|||
assign rs3 = instr_i[`REG_S3];
|
||||
|
||||
// log execution
|
||||
always @(negedge clk_i) begin
|
||||
always @(posedge clk_i) begin
|
||||
instr_trace_t trace;
|
||||
mem_acc_t mem_acc;
|
||||
// special case for WFI because we don't wait for unstalling there
|
||||
if ((id_valid_i || mret_insn_i || ecall_insn_i || pipe_flush_i || ebrk_insn_i ||
|
||||
dret_insn_i || csr_status_i || ex_data_req_i) && is_decoding_i) begin
|
||||
if (valid_i) begin
|
||||
trace = new ();
|
||||
|
||||
trace.simtime = $time;
|
||||
|
|
@ -410,38 +401,11 @@ module ibex_tracer #(
|
|||
|
||||
// replace register written back
|
||||
foreach(trace.regs_write[i]) begin
|
||||
if ((trace.regs_write[i].addr == ex_reg_addr_i) && ex_reg_we_i) begin
|
||||
if ((trace.regs_write[i].addr == ex_reg_addr_i)) begin
|
||||
trace.regs_write[i].value = ex_reg_wdata_i;
|
||||
end
|
||||
end
|
||||
// look for data accesses and log them
|
||||
if (ex_data_req_i) begin
|
||||
|
||||
if (!ex_data_gnt_i) begin
|
||||
//we wait until the the gnt comes
|
||||
do @(negedge clk_i);
|
||||
while (!ex_data_gnt_i);
|
||||
end
|
||||
|
||||
mem_acc.addr = ex_data_addr_i;
|
||||
mem_acc.we = ex_data_we_i;
|
||||
|
||||
if (mem_acc.we) begin
|
||||
mem_acc.wdata = ex_data_wdata_i;
|
||||
end else begin
|
||||
mem_acc.wdata = 'x;
|
||||
end
|
||||
//we wait until the the data instruction ends
|
||||
do @(negedge clk_i);
|
||||
while (!lsu_data_valid_i);
|
||||
|
||||
if (!mem_acc.we) begin
|
||||
//load operations
|
||||
foreach(trace.regs_write[i])
|
||||
trace.regs_write[i].value = lsu_reg_wdata_i;
|
||||
end
|
||||
trace.mem_access.push_back(mem_acc);
|
||||
end
|
||||
trace.printInstrTrace();
|
||||
end
|
||||
end // always @ (posedge clk_i)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue