added VERILATOR ifdef and fix regfile ff

controller.sv

@@ -464,8 +464,8 @@ module zeroriscy_controller
   //----------------------------------------------------------------------------
   // Assertions
   //----------------------------------------------------------------------------
-
+`ifndef VERILATOR
   assert property (
     @(posedge clk) (~(dbg_req_i & ext_req_i)) ) else $warning("Both dbg_req_i and ext_req_i are active");
-
+`endif
 endmodule // controller

debug_unit.sv

@@ -472,7 +472,7 @@ module zeroriscy_debug_unit
   //----------------------------------------------------------------------------
   // Assertions
   //----------------------------------------------------------------------------
-
+`ifndef VERILATOR
   // check that no registers are accessed when we are not in debug mode
   assert property (
     @(posedge clk) (debug_req_i) |-> ((debug_halted_o == 1'b1) ||
@@ -484,5 +484,5 @@ module zeroriscy_debug_unit
   // check that all accesses are word-aligned
   assert property (
     @(posedge clk) (debug_req_i) |-> (debug_addr_i[1:0] == 2'b00) );
-
+`endif
 endmodule // debug_unit

id_stage.sv

@@ -769,7 +769,7 @@ module zeroriscy_id_stage
   //----------------------------------------------------------------------------
   // Assertions
   //----------------------------------------------------------------------------
-
+`ifndef VERILATOR
   // make sure that branch decision is valid when jumping
   assert property (
     @(posedge clk) (branch_in_ex_o) |-> (branch_decision_i !== 1'bx) ) else $display("Branch decision is X");
@@ -786,9 +786,7 @@ module zeroriscy_id_stage
   // make sure multicycles enable signals are unique
   assert property (
     @(posedge clk) ~(data_req_ex_o & multdiv_int_en )) else $display("Multicycles enable signals are not unique");
-/*
-  // make sure no reg x16...x31 are accessed if RV32E is active
-  assert property (
-    @(posedge clk) ~(illegal_reg_rv32e)) else $display("Access to x16....x31 registers at time %t", $time);
-*/
+
+`endif
+
 endmodule

if_stage.sv

@@ -271,15 +271,11 @@ module zeroriscy_if_stage
         //----------------------------------------------------------------------------
         // Assertions
         //----------------------------------------------------------------------------
-
+`ifndef VERILATOR
         // there should never be a grant when there is no request
         assert property (
           @(posedge clk) (instr_gnt_i) |-> (instr_req_o) )
         else $warning("There was a grant without a request");
-
-        // make sure LSB of fetch_addr_n is always 0
-        assert property (
-          @(posedge clk) (req_i) |-> (~fetch_addr_n[0]) )
-        else $warning("There was a request while the fetch_addr_n LSB is set");
+`endif
 
         endmodule

load_store_unit.sv

@@ -477,7 +477,7 @@ module zeroriscy_load_store_unit
   //////////////////////////////////////////////////////////////////////////////
   // Assertions
   //////////////////////////////////////////////////////////////////////////////
-
+`ifndef VERILATOR
   // make sure there is no new request when the old one is not yet completely done
   // i.e. it should not be possible to get a grant without an rvalid for the
   // last request
@@ -493,5 +493,5 @@ module zeroriscy_load_store_unit
 
   // assert that the address does not contain X when request is sent
   assert property ( @(posedge clk) (data_req_o) |-> (!$isunknown(data_addr_o)) );
-
+`endif
 endmodule

prefetch_buffer.sv

@@ -225,10 +225,10 @@ module zeroriscy_fetch_fifo
   //----------------------------------------------------------------------------
   // Assertions
   //----------------------------------------------------------------------------
-
+`ifndef VERILATOR
   assert property (
     @(posedge clk) (in_valid_i) |-> ((valid_Q[DEPTH-1] == 1'b0) || (clear_i == 1'b1)) );
-
+`endif
 endmodule
 
 

register_file_ff.sv

@@ -83,7 +83,8 @@ module zeroriscy_register_file
         if (rst_n==1'b0) begin
           rf_reg[i] <= 'b0;
         end else begin
-          rf_reg[i] <= wdata_a_i;
+          if (we_a_dec[i])
+            rf_reg[i] <= wdata_a_i;
         end
       end