Remove LSU write offset when ONLY_ALIGNED

decoder.sv

@@ -117,7 +117,10 @@ module riscv_decoder
   `endif // PREPOST_SUPPORT
   output logic [1:0]  data_type_o,             // data type on data memory: byte, half word or word
   output logic        data_sign_extension_o,   // sign extension on read data from data memory
+  // CONFIG_REGION: ONLY_ALIGNED
+  `ifndef ONLY_ALIGNED
   output logic [1:0]  data_reg_offset_o,       // offset in byte inside register for stores
+  `endif // ONLY_ALIGNED
   output logic        data_load_event_o,       // data request is in the special event range
 
   // CONFIG_REGION: HWLP_SUPPORT
@@ -217,7 +220,10 @@ module riscv_decoder
     data_we_o                   = 1'b0;
     data_type_o                 = 2'b00;
     data_sign_extension_o       = 1'b0;
+    // CONFIG_REGION: ONLY_ALIGNED
+    `ifndef ONLY_ALIGNED
     data_reg_offset_o           = 2'b00;
+    `endif // ONLY_ALIGNED
     data_req                    = 1'b0;
     data_load_event_o           = 1'b0;
 

id_stage.sv

@@ -181,7 +181,10 @@ module riscv_id_stage
     output logic        data_we_ex_o,
     output logic [1:0]  data_type_ex_o,
     output logic        data_sign_ext_ex_o,
+    // CONFIG_REGION: ONLY_ALIGNED
+    `ifndef ONLY_ALIGNED
     output logic [1:0]  data_reg_offset_ex_o,
+    `endif // ONLY_ALIGNED
     output logic        data_load_event_ex_o,
 
     // CONFIG_REGION: ONLY_ALIGNED
@@ -369,7 +372,10 @@ module riscv_id_stage
   logic        data_we_id;
   logic [1:0]  data_type_id;
   logic        data_sign_ext_id;
+  // CONFIG_REGION: ONLY_ALIGNED
+  `ifndef ONLY_ALIGNED
   logic [1:0]  data_reg_offset_id;
+  `endif // ONLY_ALIGNED
   logic        data_req_id;
   logic        data_load_event_id;
 
@@ -1088,7 +1094,10 @@ module riscv_id_stage
     `endif // PREPOST_SUPPORT
     .data_type_o                     ( data_type_id              ),
     .data_sign_extension_o           ( data_sign_ext_id          ),
+    // CONFIG_REGION: ONLY_ALIGNED
+    `ifndef ONLY_ALIGNED
     .data_reg_offset_o               ( data_reg_offset_id        ),
+    `endif // ONLY_ALIGNED
     .data_load_event_o               ( data_load_event_id        ),
 
 
@@ -1393,7 +1402,10 @@ always_ff @(posedge clk, negedge rst_n)
       data_we_ex_o                <= 1'b0;
       data_type_ex_o              <= 2'b0;
       data_sign_ext_ex_o          <= 1'b0;
+      // CONFIG_REGION: ONLY_ALIGNED
+      `ifndef ONLY_ALIGNED
       data_reg_offset_ex_o        <= 2'b0;
+      `endif // ONLY_ALIGNED
       data_req_ex_o               <= 1'b0;
       data_load_event_ex_o        <= 1'b0;
       // CONFIG_REGION: ONLY_ALIGNED
@@ -1511,7 +1523,10 @@ always_ff @(posedge clk, negedge rst_n)
           data_we_ex_o              <= data_we_id;
           data_type_ex_o            <= data_type_id;
           data_sign_ext_ex_o        <= data_sign_ext_id;
+          // CONFIG_REGION: ONLY_ALIGNED
+          `ifndef ONLY_ALIGNED
           data_reg_offset_ex_o      <= data_reg_offset_id;
+          `endif // ONLY_ALIGNED
           data_load_event_ex_o      <= data_load_event_id;
         end else begin
           data_load_event_ex_o      <= 1'b0;

load_store_unit.sv

@@ -47,7 +47,10 @@ module riscv_load_store_unit
     input  logic         data_we_ex_i,         // write enable                      -> from ex stage
     input  logic [1:0]   data_type_ex_i,       // Data type word, halfword, byte    -> from ex stage
     input  logic [31:0]  data_wdata_ex_i,      // data to write to memory           -> from ex stage
+    // CONFIG_REGION: ONLY_ALIGNED
+    `ifndef ONLY_ALIGNED
     input  logic [1:0]   data_reg_offset_ex_i, // offset inside register for stores -> from ex stage
+    `endif // ONLY_ALIGNED
     input  logic         data_sign_ext_ex_i,   // sign extension                    -> from ex stage
 
     output logic [31:0]  data_rdata_ex_o,      // requested data                    -> to ex stage
@@ -178,7 +181,12 @@ module riscv_load_store_unit
   // prepare data to be written to the memory
   // we handle misaligned accesses, half word and byte accesses and
   // register offsets here
+  // CONFIG_REGION: ONLY_ALIGNED
+  `ifndef ONLY_ALIGNED
   assign wdata_offset = data_addr_int[1:0] - data_reg_offset_ex_i[1:0];
+  `else 
+  assign wdata_offset = data_addr_int[1:0];
+  `endif // ONLY_ALIGNED
   always_comb
   begin
     case (wdata_offset)

riscv_core.sv

@@ -216,7 +216,10 @@ module riscv_core
   logic        data_we_ex;
   logic [1:0]  data_type_ex;
   logic        data_sign_ext_ex;
+  // CONFIG_REGION: ONLY_ALIGNED
+  `ifndef ONLY_ALIGNED
   logic [1:0]  data_reg_offset_ex;
+  `endif // ONLY_ALIGNED
   logic        data_req_ex;
   logic [31:0] data_pc_ex;
   logic        data_load_event_ex;
@@ -554,7 +557,10 @@ module riscv_core
     .data_we_ex_o                 ( data_we_ex           ), // to load store unit
     .data_type_ex_o               ( data_type_ex         ), // to load store unit
     .data_sign_ext_ex_o           ( data_sign_ext_ex     ), // to load store unit
+    // CONFIG_REGION: ONLY_ALIGNED
+    `ifndef ONLY_ALIGNED
     .data_reg_offset_ex_o         ( data_reg_offset_ex   ), // to load store unit
+    `endif // ONLY_ALIGNED
     .data_load_event_ex_o         ( data_load_event_ex   ), // to load store unit
 
     // CONFIG_REGION: ONLY_ALIGNED
@@ -741,7 +747,10 @@ module riscv_core
     .data_we_ex_i          ( data_we_ex         ),
     .data_type_ex_i        ( data_type_ex       ),
     .data_wdata_ex_i       ( alu_operand_c_ex   ),
+    // CONFIG_REGION: ONLY_ALIGNED
+    `ifndef ONLY_ALIGNED
     .data_reg_offset_ex_i  ( data_reg_offset_ex ),
+    `endif // ONLY_ALIGNED
     .data_sign_ext_ex_i    ( data_sign_ext_ex   ),  // sign extension
 
     .data_rdata_ex_o       ( regfile_wdata      ),