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[dv/ibex] Enable icache in Ibex environment

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Signed-off-by: Udi Jonnalagadda <udij@google.com>
This commit is contained in:
Udi Jonnalagadda 2020-10-16 17:23:32 -07:00 • committed by Philipp Wagner
parent 9b656a0a2c
commit 04e720d6da
9 changed files with 74 additions and 15 deletions
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8
doc/03_reference/verification.rst
View file

@ -74,7 +74,7 @@ Testplan
""""""""
The goal of this bench is to fully verify the Ibex core with 100%
coverage. This includes testing all RV32IMC instructions, privileged
coverage. This includes testing all RV32IMCB instructions, privileged
spec compliance, exception and interrupt testing, Debug Mode operation etc.
The complete test list can be found in the file `dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml>`_.
@ -92,8 +92,8 @@ In order to run the co-simulation flow, you'll need:
- A SystemVerilog simulator that supports UVM. The flow is currently
tested with VCS.
- A RISC-V instruction set simulator. For example, Spike_ or
OVPsim_. Note that Spike must be configured with
- A RISC-V instruction set simulator, such as Spike_ or OVPsim_.
Note that Spike must be configured with
``--enable-commitlog`` and ``--enable-misaligned``. The commit log
is needed to track the instructions that were executed and
``--enable-misaligned`` tells Spike to simulate a core that
@ -101,6 +101,8 @@ In order to run the co-simulation flow, you'll need:
trap handler).
In addition, Spike does not support the `RISC-V Bit Manipulation Extension <bitmanip_>`_ (Bitmanip) by default.
To support this draft extension implemented in Ibex, the `riscv-bitmanip branch <Spike_>`_ of Spike needs to be used.
If it is desired to simulate the core with the Icache enabled, a lowRISC-specific branch
of Spike must be used, `found here <https://github.com/lowRISC/riscv-isa-sim/tree/ibex>`_.
- A working RISC-V toolchain (to compile / assemble the generated programs before simulating them).
Either download a `pre-built toolchain <riscv-toolchain-releases_>`_ (quicker) or download and build the `RISC-V GNU compiler toolchain <riscv-toolchain-source_>`_.

14
dv/riscv_compliance/ibex_riscv_compliance.core
View file

@ -48,6 +48,18 @@ parameters:
paramtype: vlogdefine
description: "Register file implementation parameter enum. See the ibex_pkg::regfile_e enum in ibex_pkg.sv for permitted values."
ICache:
datatype: int
default: 0
paramtype: vlogparam
description: "Enable instruction cache"
ICacheECC:
datatype: int
default: 0
paramtype: vlogparam
description: "Enable ECC protection in instruction cache"
BranchTargetALU:
datatype: int
paramtype: vlogparam
@ -95,6 +107,8 @@ targets:
- RV32M
- RV32B
- RegFile
- ICache
- ICacheECC
- BranchTargetALU
- WritebackStage
- BranchPredictor

4
dv/uvm/core_ibex/Makefile
View file

@ -36,7 +36,7 @@ COV := 0
# RTL simulator
SIMULATOR := vcs
# ISS (spike, ovpsim)
ISS := ovpsim
ISS := spike
# ISS runtime options
ISS_OPTS :=
# ISA
@ -65,7 +65,7 @@ PMP_REGIONS := 16
# PMP Granularity
PMP_GRANULARITY := 0
IBEX_CONFIG := experimental-maxperf-pmp-bmfull
IBEX_CONFIG := experimental-maxperf-pmp-bmfull-icache
# TODO(udinator) - might need options for SAIL/Whisper/Spike
ifeq (${ISS},ovpsim)

23
dv/uvm/core_ibex/common/prim/prim_ram_1p.sv
View file

@ -8,15 +8,17 @@
// Its contents are taken from the file which would be generated by FuseSoC.
// https://github.com/lowRISC/ibex/issues/893
`ifndef PRIM_DEFAULT_IMPL
`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
`endif
module prim_ram_1p
#(
module prim_ram_1p #(
parameter int Width = 32, // bit
parameter int Depth = 128,
parameter int DataBitsPerMask = 1, // Number of data bits per bit of write mask
parameter MemInitFile = "", // VMEM file to initialize the memory width
localparam int Aw = $clog2(Depth) // derived parameter
) (
input logic clk_i,
@ -27,14 +29,17 @@ module prim_ram_1p #(
input logic [Width-1:0] wmask_i,
output logic [Width-1:0] rdata_o // Read data. Data is returned one cycle after req_i is high.
);
parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
if (Impl == prim_pkg::ImplGeneric) begin : gen_generic
prim_generic_ram_1p u_impl_generic (
if (1) begin : gen_generic
prim_generic_ram_1p #(
.Depth(Depth),
.MemInitFile(MemInitFile),
.Width(Width),
.DataBitsPerMask(DataBitsPerMask)
) u_impl_generic (
.*
);
end else begin : gen_failure
// TODO: Find code that works across tools and causes a compile failure
end
endmodule

2
dv/uvm/core_ibex/riscv_dv_extension/csr_description.yaml
View file

@ -329,7 +329,7 @@
- field_name: icache_enable
description: >
Enable or disable the instruction cache
type: R
type: WARL
reset_val: 0
msb: 0
lsb: 0

5
dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv
View file

@ -34,4 +34,9 @@ class ibex_asm_program_gen extends riscv_asm_program_gen;
instr_stream.push_back("_start:");
endfunction
virtual function void init_custom_csr(ref string instr[$]);
// Write 1 to cpuctrl.icache_enable to enable Icache during simulation
instr.push_back("csrwi 0x7c0, 1");
endfunction
endclass

4
dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
View file

@ -54,6 +54,8 @@ module core_ibex_tb_top;
parameter ibex_pkg::regfile_e RegFile = `IBEX_CFG_RegFile;
parameter bit BranchTargetALU = 1'b0;
parameter bit WritebackStage = 1'b0;
parameter bit ICache = 1'b0;
parameter bit ICacheECC = 1'b0;
parameter bit BranchPredictor = 1'b0;
ibex_core_tracing #(
@ -68,6 +70,8 @@ module core_ibex_tb_top;
.RegFile (RegFile ),
.BranchTargetALU (BranchTargetALU ),
.WritebackStage (WritebackStage ),
.ICache (ICache ),
.ICacheECC (ICacheECC ),
.BranchPredictor (BranchPredictor )
) dut (
.clk_i (clk ),

27
ibex_configs.yaml
View file

@ -14,6 +14,8 @@ small:
RegFile : "ibex_pkg::RegFileFF"
BranchTargetALU : 0
WritebackStage : 0
ICache : 0
ICacheECC : 0
BranchPredictor : 0
PMPEnable : 0
PMPGranularity : 0
@ -33,6 +35,8 @@ experimental-maxperf:
RegFile : "ibex_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
ICacheECC : 0
BranchPredictor : 0
PMPEnable : 0
PMPGranularity : 0
@ -46,6 +50,8 @@ experimental-maxperf-pmp:
RegFile : "ibex_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
ICacheECC : 0
BranchPredictor : 0
PMPEnable : 1
PMPGranularity : 0
@ -59,6 +65,8 @@ experimental-maxperf-pmp-bmbalanced:
RegFile : "ibex_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
ICacheECC : 0
BranchPredictor : 0
PMPEnable : 1
PMPGranularity : 0
@ -72,6 +80,23 @@ experimental-maxperf-pmp-bmfull:
RegFile : "ibex_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
ICacheECC : 0
BranchPredictor : 0
PMPEnable : 1
PMPGranularity : 0
PMPNumRegions : 16
# experimental-maxperf-pmp-bmfull config above with icache enabled
experimental-maxperf-pmp-bmfull-icache:
RV32E : 0
RV32M : "ibex_pkg::RV32MSingleCycle"
RV32B : "ibex_pkg::RV32BFull"
RegFile : "ibex_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 1
ICacheECC : 1
BranchPredictor : 0
PMPEnable : 1
PMPGranularity : 0
@ -88,6 +113,8 @@ experimental-branch-predictor:
RegFile : "ibex_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
ICacheECC : 0
BranchPredictor : 1
PMPEnable : 0
PMPGranularity : 0

2
ibex_core_tracing.core
View file

@ -118,6 +118,8 @@ targets:
- RV32M
- RV32B
- RegFile
- ICache
- ICacheECC
- BranchTargetALU
- WritebackStage
- BranchPredictor