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https://github.com/lowRISC/ibex.git
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Make illegal instruction exceptions work again
This commit is contained in:
Andreas Traber
parent
e41c7b96be
commit
0608b98440
5 changed files with 42 additions and 45 deletions
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@ -46,6 +46,7 @@ module controller
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input logic instr_ack_i, // Acknow from instr memory or cache (means that data is available)
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output logic [2:0] pc_mux_sel_o, // Selector in the Fetch stage to select the rigth PC (normal, jump ...)
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output logic pc_set_o, // jump to address set by pc_mux_sel
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// ALU signals
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output logic [`ALU_OP_WIDTH-1:0] alu_operator_o, // Operator in the Ex stage for the ALU block
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@ -99,6 +100,7 @@ module controller
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input logic irq_present_i, // there is an IRQ, so if we are sleeping we should wake up now
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// Exception Controller Signals
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input logic exc_pc_sel_i, // exception execution requested
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input logic illegal_c_insn_i, // compressed instruction decode failed
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output logic illegal_insn_o, // illegal instruction encountered
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output logic trap_insn_o, // trap instruction encountered
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@ -142,7 +144,7 @@ module controller
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);
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// FSM state encoding
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enum logic [3:0] { RESET, BOOT_SET, SLEEP, FIRST_FETCH, DECODE, BRANCH, BRANCH_DELAY,
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enum logic [3:0] { RESET, BOOT_SET, SLEEP, FIRST_FETCH, DECODE, BRANCH,
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FLUSH_EX, FLUSH_WB,
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DBG_FLUSH_EX, DBG_FLUSH_WB, DBG_SIGNAL, DBG_WAIT } ctrl_fsm_cs, ctrl_fsm_ns;
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@ -166,6 +168,7 @@ module controller
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logic pipe_flush;
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logic trap_insn;
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logic eret_insn;
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logic [1:0] jump_in_id;
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@ -243,6 +246,7 @@ module controller
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illegal_insn_int = 1'b0;
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trap_insn = 1'b0;
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eret_insn = 1'b0;
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pipe_flush = 1'b0;
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rega_used = 1'b0;
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@ -789,8 +793,7 @@ module controller
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32'h10_00_00_73: // ERET
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begin
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// TODO: Handle in controller
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//pc_mux_sel = `PC_ERET;
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eret_insn = 1'b1;
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clear_isr_running_o = 1'b1;
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end
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@ -960,6 +963,7 @@ module controller
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instr_req_o = 1'b1;
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pc_mux_sel_o = `PC_BOOT;
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pc_set_o = 1'b0;
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ctrl_fsm_ns = ctrl_fsm_cs;
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@ -987,6 +991,7 @@ module controller
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begin
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instr_req_o = 1'b1;
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pc_mux_sel_o = `PC_BOOT;
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pc_set_o = 1'b1;
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ctrl_fsm_ns = FIRST_FETCH;
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end
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@ -1015,8 +1020,10 @@ module controller
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// hwloop detected, jump to start address!
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// Attention: This has to be done in the DECODE and the FIRST_FETCH states
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if (hwloop_jump_i == 1'b1)
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if (hwloop_jump_i == 1'b1) begin
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pc_mux_sel_o = `PC_HWLOOP;
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pc_set_o = 1'b1;
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end
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end
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DECODE:
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@ -1035,8 +1042,9 @@ module controller
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if (jump_in_id == `BRANCH_JALR || jump_in_id == `BRANCH_JAL) begin
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pc_mux_sel_o = `PC_JUMP;
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if (~stall_id_o)
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ctrl_fsm_ns = DECODE;
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// we don't have to change our current state here as the prefetch
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// buffer is automatically invalidated, thus the next instruction
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// that is served to the ID stage is the one of the jump target
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end
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// handle hwloops
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@ -1049,6 +1057,21 @@ module controller
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illegal_insn_o = 1'b1;
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end
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if (exc_pc_sel_i) begin
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pc_mux_sel_o = `PC_EXCEPTION;
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pc_set_o = 1'b1;
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// we don't have to change our current state here as the prefetch
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// buffer is automatically invalidated, thus the next instruction
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// that is served to the ID stage is the one of the jump to the
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// exception handler
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end
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if (eret_insn) begin
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pc_mux_sel_o = `PC_ERET;
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pc_set_o = 1'b1;
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end
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// handle WFI instruction, flush pipeline and (potentially) go to
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// sleep
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if (pipe_flush || exc_pipe_flush_i)
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@ -1107,25 +1130,6 @@ module controller
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end
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end
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// "delay slot" of jump and branch
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// inserts a nop by not decoding the instruction
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BRANCH_DELAY:
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begin
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// if we want to debug, flush the pipeline
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// the current_pc_if will take the value of the next instruction to
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// be executed (NPC)
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if (trap_hit_i)
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begin
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halt_if = 1'b1;
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halt_id = 1'b1;
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ctrl_fsm_ns = DBG_FLUSH_EX;
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end else begin
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if (~stall_id_o)
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ctrl_fsm_ns = DECODE;
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end
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end
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DBG_FLUSH_EX:
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begin
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halt_if = 1'b1;
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@ -1161,6 +1165,7 @@ module controller
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if(dbg_set_npc_i == 1'b1) begin
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halt_id = 1'b0;
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pc_mux_sel_o = `PC_DBG_NPC;
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pc_set_o = 1'b1;
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ctrl_fsm_ns = DBG_WAIT;
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end
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@ -34,7 +34,6 @@ module exc_controller
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// to IF stage
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output logic exc_pc_sel_o, // influences next PC, if set exception PC is used
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output logic [1:0] exc_pc_mux_o, // Selector in the Fetch stage to select the rigth exception PC
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output logic force_nop_o, // Force a Nop (Bubble) in the Fetch stage
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// hwloop signals
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output logic hwloop_enable_o, // '1' if pc is valid (interrupt related signal)
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@ -78,7 +77,7 @@ module exc_controller
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logic clear_exc_reason;
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// disable hardware loops when nops are inserted or the controller is not active
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assign hwloop_enable_o = (~force_nop_o) | (~core_busy_i);
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assign hwloop_enable_o = (~core_busy_i);
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/////////////////////////////////////////////
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// ____ _ //
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@ -162,7 +161,6 @@ module exc_controller
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clear_exc_reason = 1'b0;
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save_pc_if_o = 1'b0;
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save_pc_id_o = 1'b0;
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force_nop_o = 1'b0;
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pc_valid_o = 1'b1;
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exc_pc_sel_o = 1'b0;
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exc_pc_mux_o = `EXC_PC_NO_INCR;
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@ -179,7 +177,6 @@ module exc_controller
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ExcIR: begin
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if (jump_in_id_i == 2'b00)
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begin // no delay slot
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force_nop_o = 1'b1;
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exc_pc_sel_o = 1'b1;
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save_pc_if_o = 1'b1; // save current PC
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@ -201,7 +198,6 @@ module exc_controller
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// Illegal instruction encountered, we directly jump to
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// the ISR without flushing the pipeline
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ExcIllegalInsn: begin
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force_nop_o = 1'b1;
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exc_pc_sel_o = 1'b1;
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exc_pc_mux_o = `EXC_PC_ILLINSN;
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save_pc_id_o = 1'b1; // save current PC
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@ -217,7 +213,6 @@ module exc_controller
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// Execute delay slot for IR
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NopDelayIR:
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begin
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force_nop_o = 1'b1;
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exc_pc_sel_o = 1'b1;
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save_pc_if_o = 1'b1; // save current PC
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11
id_stage.sv
11
id_stage.sv
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@ -55,9 +55,9 @@ module id_stage
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output logic [31:0] jump_target_o,
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// IF and ID stage signals
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output logic pc_set_o,
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output logic [2:0] pc_mux_sel_o,
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output logic [1:0] exc_pc_mux_o,
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output logic force_nop_o,
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input logic illegal_c_insn_i,
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@ -169,8 +169,6 @@ module id_stage
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logic exc_pc_sel;
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logic [2:0] pc_mux_sel_int; // selects next PC in if stage
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logic force_nop_exc;
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logic irq_present;
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// Signals running between controller and exception controller
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@ -267,8 +265,7 @@ module id_stage
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logic [31:0] operand_c;
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assign force_nop_o = force_nop_exc;
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assign pc_mux_sel_o = (exc_pc_sel == 1'b1) ? `PC_EXCEPTION : pc_mux_sel_int;
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assign pc_mux_sel_o = pc_mux_sel_int;
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assign instr = instr_rdata_i;
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@ -538,6 +535,8 @@ module id_stage
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.instr_req_o ( instr_req_o ),
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.instr_gnt_i ( instr_gnt_i ),
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.instr_ack_i ( instr_ack_i ),
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.pc_set_o ( pc_set_o ),
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.pc_mux_sel_o ( pc_mux_sel_int ),
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// Alu signals
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@ -592,6 +591,7 @@ module id_stage
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.irq_present_i ( irq_present ),
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// Exception Controller Signals
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.exc_pc_sel_i ( exc_pc_sel ),
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.illegal_c_insn_i ( illegal_c_insn_i ),
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.illegal_insn_o ( illegal_insn ),
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.trap_insn_o ( trap_insn ),
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@ -662,7 +662,6 @@ module id_stage
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// to IF stage
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.exc_pc_sel_o ( exc_pc_sel ),
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.exc_pc_mux_o ( exc_pc_mux_o ),
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.force_nop_o ( force_nop_exc ),
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// hwloop signals
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.hwloop_enable_o ( hwloop_enable ),
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@ -60,7 +60,7 @@ module if_stage
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output logic [31:0] current_pc_id_o,
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// Forwarding ports - control signals
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input logic force_nop_i, // insert a NOP in the pipe
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input logic pc_set_i, // set the program counter to a new value
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input logic [31:0] exception_pc_reg_i, // address used to restore PC when the interrupt/exception is served
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input logic [2:0] pc_mux_sel_i, // sel for pc multiplexer
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input logic [1:0] exc_pc_mux_i, // select which exception to execute
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@ -78,7 +78,6 @@ module if_stage
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// from debug unit
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input logic [31:0] dbg_npc_i,
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input logic dbg_set_npc_i,
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// pipeline stall
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input logic stall_if_i,
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@ -320,7 +319,7 @@ module if_stage
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end
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end else if (jump_in_id_i == `BRANCH_JAL || jump_in_id_i == `BRANCH_JALR
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|| dbg_set_npc_i
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|| pc_set_i
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|| hwloop_jump_i) begin
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valid_o = 1'b0;
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@ -86,7 +86,7 @@ module riscv_core
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logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage
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logic [31:0] current_pc_if; // Current Program counter
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logic [31:0] current_pc_id; // Current Program counter
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logic force_nop_id;
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logic pc_set;
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logic [2:0] pc_mux_sel_id; // Mux selector for next PC
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logic [1:0] exc_pc_mux_id; // Mux selector for exception PC
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@ -248,8 +248,8 @@ module riscv_core
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.current_pc_if_o ( current_pc_if ), // current pc in IF stage
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.current_pc_id_o ( current_pc_id ), // current pc in ID stage
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// Forwrding ports - control signals
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.force_nop_i ( force_nop_id ), // select incoming instr or NOP
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// control signals
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.pc_set_i ( pc_set ),
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.exception_pc_reg_i ( epcr ), // Exception PC register
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.pc_mux_sel_i ( pc_mux_sel_id ), // sel for pc multiplexer
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.exc_pc_mux_i ( exc_pc_mux_id ), // selector for exception multiplexer
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@ -260,7 +260,6 @@ module riscv_core
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// from debug unit
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.dbg_npc_i ( dbg_npc ),
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.dbg_set_npc_i ( dbg_set_npc ),
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// Jump and branch target and decision
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.jump_in_id_i ( jump_in_id ),
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@ -308,9 +307,9 @@ module riscv_core
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.instr_gnt_i ( instr_grant_i ),
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.instr_ack_i ( instr_ack_int ),
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.pc_set_o ( pc_set ),
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.pc_mux_sel_o ( pc_mux_sel_id ),
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.exc_pc_mux_o ( exc_pc_mux_id ),
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.force_nop_o ( force_nop_id ),
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.illegal_c_insn_i ( illegal_c_insn_id ),
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