github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-24 22:07:43 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fix syntax

Browse source
This commit is contained in:
Markus Wegmann 2016-12-15 16:27:10 +01:00
parent d871d1a590
commit 0733e7e14e
3 changed files with 13 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

6
controller.sv
View file

@ -545,8 +545,14 @@ module riscv_controller
deassert_we_o = 1'b1;
// Stall because of load operation
// CONFIG_REGION: THREE_PORT_REG_FILE
`ifdef THREE_PORT_REG_FILE
if ((data_req_ex_i == 1'b1) && (regfile_we_ex_i == 1'b1) &&
((reg_d_ex_is_reg_a_i == 1'b1) || (reg_d_ex_is_reg_b_i == 1'b1) || (reg_d_ex_is_reg_c_i == 1'b1)) )
`else
if ((data_req_ex_i == 1'b1) && (regfile_we_ex_i == 1'b1) &&
((reg_d_ex_is_reg_a_i == 1'b1) || (reg_d_ex_is_reg_b_i == 1'b1)) )
`endif // THREE_PORT_REG_FILE
begin
deassert_we_o = 1'b1;
load_stall_o = 1'b1;

14
decoder.sv
View file

@ -69,10 +69,7 @@ module riscv_decoder
output logic [ALU_OP_WIDTH-1:0] alu_operator_o, // ALU operation selection
output logic [2:0] alu_op_a_mux_sel_o, // operand a selection: reg value, PC, immediate or zero
output logic [2:0] alu_op_b_mux_sel_o, // operand b selection: reg value or immediate
// CONFIG_REGION: THREE_PORT_REG_FILE
`ifdef THREE_PORT_REG_FILE
output logic [1:0] alu_op_c_mux_sel_o, // operand c selection: reg value or jump target
`endif // THREE_PORT_REG_FILE
// CONFIG_REGION: VEC_SUPPORT
`ifdef VEC_SUPPORT
@ -168,16 +165,17 @@ module riscv_decoder
alu_operator_o = ALU_SLTU;
alu_op_a_mux_sel_o = OP_A_REGA_OR_FWD;
alu_op_b_mux_sel_o = OP_B_REGB_OR_FWD;
// CONFIG_REGION: THREE_PORT_REG_FILE
`ifdef THREE_PORT_REG_FILE
alu_op_c_mux_sel_o = OP_C_REGC_OR_FWD;
`endif // THREE_PORT_REG_FILE
// CONFIG_REGION: VEC_SUPPORT
`ifdef VEC_SUPPORT
alu_vec_mode_o = VEC_MODE32;
scalar_replication_o = 1'b0;
`endif // VEC_SUPPORT
// CONFIG_REGION: THREE_PORT_REG_FILE
`ifdef THREE_PORT_REG_FILE
regc_mux_o = REGC_ZERO;
`endif // THREE_PORT_REG_FILE
imm_a_mux_sel_o = IMMA_ZERO;
imm_b_mux_sel_o = IMMB_I;
@ -287,10 +285,8 @@ module riscv_decoder
OPCODE_BRANCH: begin // Branch
jump_target_mux_sel_o = JT_COND;
jump_in_id = BRANCH_COND;
// CONFIG_REGION: THREE_PORT_REG_FILE
`ifdef THREE_PORT_REG_FILE
alu_op_c_mux_sel_o = OP_C_JT;
`endif // THREE_PORT_REG_FILE
rega_used_o = 1'b1;
regb_used_o = 1'b1;

4
id_stage.sv
View file

@ -642,8 +642,8 @@ module riscv_id_stage #(
// | |_| | |_) | __/ | | (_| | | | | (_| | / ___ \ //
// \___/| .__/ \___|_| \__,_|_| |_|\__,_| /_/ \_\ //
// |_| //
///////////////////////////////////////////////////////
/
////////////////////////////////////////////////////////
// ALU_Op_a Mux
always_comb
begin : alu_operand_a_mux