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[rtl] Remove X assignments, add SVAs for selector signals

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This commit replaces all X assignments in the RTL with defined
values. In addition, SystemVerilog Assertions are added to catch
invalid signal values in simulation. A new file containing the
corresponding assertion macros is added as well.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit is contained in:
Pirmin Vogel 2019-12-17 12:43:22 +01:00
parent b10039c4ef
commit 0778008f33
15 changed files with 366 additions and 33 deletions
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4
lint/verilator_waiver.vlt
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@ -49,10 +49,14 @@ lint_off -msg UNUSED -file "*/rtl/ibex_register_file_ff.sv" -lines 21
// Signal is not used: clk_i
// leaving clk and reset connected in-case we want to add assertions
lint_off -msg UNUSED -file "*/rtl/ibex_pmp.sv" -lines 15
lint_off -msg UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -lines 14
lint_off -msg UNUSED -file "*/rtl/ibex_decoder.sv" -lines 21
// Signal is not used: rst_ni
// leaving clk and reset connected in-case we want to add assertions
lint_off -msg UNUSED -file "*/rtl/ibex_pmp.sv" -lines 16
lint_off -msg UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -lines 15
lint_off -msg UNUSED -file "*/rtl/ibex_decoder.sv" -lines 22
// Signal unoptimizable: Feedback to clock or circular logic:
// ibex_core.cs_registers_i.mie_q