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[rtl] Rework access to performance counter CSRs

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This commit reworks the code section describing how the performance
counter CSRs are accessed by CSR instructions. Instead of using an
address mask inside the default case, and excluding CSRs in the same
address range previously handled (like `mcycle(h)`, `minstret(h)`,
`mcountinhibit`), all performance counter CSRs are now explicitly
enumerated. This enhances readability of the code and enhances
compatibility with some tools without changing behavior or causing
lint problems.

This commit is based on suggestions from @MarekPikula. It replaces the
proposal in lowRISC/ibex#336.
This commit is contained in:
Pirmin Vogel 2019-10-31 13:23:23 +00:00
parent 2041f10c69
commit 0a1a8514c4
2 changed files with 159 additions and 56 deletions
Download patch file Download diff file Expand all files Collapse all files

112
rtl/ibex_cs_registers.sv
View file

@ -207,6 +207,7 @@ module ibex_cs_registers #(
logic illegal_csr_write;
logic [7:0] unused_boot_addr;
logic [2:0] unused_csr_addr;
assign unused_boot_addr = boot_addr_i[7:0];
@ -216,6 +217,7 @@ module ibex_cs_registers #(
logic [$bits(csr_num_e)-1:0] csr_addr;
assign csr_addr = {csr_addr_i};
assign unused_csr_addr = csr_addr[7:5];
assign mhpmcounter_idx = csr_addr[4:0];
// See RISC-V Privileged Specification, version 1.11, Section 2.1
@ -328,41 +330,45 @@ module ibex_cs_registers #(
// machine counter/timers
CSR_MCOUNTINHIBIT: csr_rdata_int = mcountinhibit;
CSR_MCYCLE: csr_rdata_int = mhpmcounter_q[0][31: 0];
CSR_MCYCLEH: csr_rdata_int = mhpmcounter_q[0][63:32];
CSR_MINSTRET: csr_rdata_int = mhpmcounter_q[2][31: 0];
CSR_MINSTRETH: csr_rdata_int = mhpmcounter_q[2][63:32];
CSR_MHPMEVENT3,
CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7,
CSR_MHPMEVENT8, CSR_MHPMEVENT9, CSR_MHPMEVENT10, CSR_MHPMEVENT11,
CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15,
CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19,
CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23,
CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27,
CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT30, CSR_MHPMEVENT31: begin
csr_rdata_int = mhpmevent[mhpmcounter_idx];
end
CSR_MCYCLE,
CSR_MINSTRET,
CSR_MHPMCOUNTER3,
CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7,
CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11,
CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15,
CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19,
CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23,
CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27,
CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: begin
csr_rdata_int = mhpmcounter_q[mhpmcounter_idx][31:0];
end
CSR_MCYCLEH,
CSR_MINSTRETH,
CSR_MHPMCOUNTER3H,
CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H,
CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H,
CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H,
CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H,
CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H,
CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H,
CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: begin
csr_rdata_int = mhpmcounter_q[mhpmcounter_idx][63:32];
end
default: begin
if ((csr_addr & CSR_MASK_MCOUNTER) == CSR_OFF_MCOUNTER_SETUP) begin
csr_rdata_int = mhpmevent[mhpmcounter_idx];
// check access to non-existent or already covered CSRs
if ((csr_addr[4:0] == 5'b00000) || // CSR_MCOUNTINHIBIT
(csr_addr[4:0] == 5'b00001) ||
(csr_addr[4:0] == 5'b00010)) begin
illegal_csr = 1'b1;
end
end else if ((csr_addr & CSR_MASK_MCOUNTER) == CSR_OFF_MCOUNTER) begin
csr_rdata_int = mhpmcounter_q[mhpmcounter_idx][31: 0];
// check access to non-existent or already covered CSRs
if ((csr_addr[4:0] == 5'b00000) || // CSR_MCYCLE
(csr_addr[4:0] == 5'b00001) ||
(csr_addr[4:0] == 5'b00010)) begin // CSR_MINSTRET
illegal_csr = 1'b1;
end
end else if ((csr_addr & CSR_MASK_MCOUNTER) == CSR_OFF_MCOUNTERH) begin
csr_rdata_int = mhpmcounter_q[mhpmcounter_idx][63:32];
// check access to non-existent or already covered CSRs
if ((csr_addr[4:0] == 5'b00000) || // CSR_MCYCLEH
(csr_addr[4:0] == 5'b00001) ||
(csr_addr[4:0] == 5'b00010)) begin // CSR_MINSTRETH
illegal_csr = 1'b1;
end
end else begin
illegal_csr = 1'b1;
end
illegal_csr = 1'b1;
end
endcase
end
@ -463,20 +469,36 @@ module ibex_cs_registers #(
CSR_DSCRATCH0: dscratch0_d = csr_wdata_int;
CSR_DSCRATCH1: dscratch1_d = csr_wdata_int;
CSR_MCOUNTINHIBIT: mcountinhibit_we = 1'b1;
CSR_MCYCLE: mhpmcounter_we[0] = 1'b1;
CSR_MCYCLEH: mhpmcounterh_we[0] = 1'b1;
CSR_MINSTRET: mhpmcounter_we[2] = 1'b1;
CSR_MINSTRETH: mhpmcounterh_we[2] = 1'b1;
// machine counter/timers
CSR_MCOUNTINHIBIT: mcountinhibit_we = 1'b1;
default: begin
// performance counters and event selector
if ((csr_addr & CSR_MASK_MCOUNTER) == CSR_OFF_MCOUNTER) begin
mhpmcounter_we[mhpmcounter_idx] = 1'b1;
end else if ((csr_addr & CSR_MASK_MCOUNTER) == CSR_OFF_MCOUNTERH) begin
mhpmcounterh_we[mhpmcounter_idx] = 1'b1;
end
CSR_MCYCLE,
CSR_MINSTRET,
CSR_MHPMCOUNTER3,
CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7,
CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11,
CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15,
CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19,
CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23,
CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27,
CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: begin
mhpmcounter_we[mhpmcounter_idx] = 1'b1;
end
CSR_MCYCLEH,
CSR_MINSTRETH,
CSR_MHPMCOUNTER3H,
CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H,
CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H,
CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H,
CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H,
CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H,
CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H,
CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: begin
mhpmcounterh_we[mhpmcounter_idx] = 1'b1;
end
default:;
endcase
end

103
rtl/ibex_pkg.sv
View file

@ -266,23 +266,104 @@ typedef enum logic[11:0] {
CSR_DSCRATCH1 = 12'h7b3, // optional
// Machine Counter/Timers
CSR_MCOUNTINHIBIT = 12'h320,
CSR_MCYCLE = 12'hB00,
CSR_MCYCLEH = 12'hB80,
CSR_MINSTRET = 12'hB02,
CSR_MINSTRETH = 12'hB82
CSR_MCOUNTINHIBIT = 12'h320,
CSR_MHPMEVENT3 = 12'h323,
CSR_MHPMEVENT4 = 12'h324,
CSR_MHPMEVENT5 = 12'h325,
CSR_MHPMEVENT6 = 12'h326,
CSR_MHPMEVENT7 = 12'h327,
CSR_MHPMEVENT8 = 12'h328,
CSR_MHPMEVENT9 = 12'h329,
CSR_MHPMEVENT10 = 12'h32A,
CSR_MHPMEVENT11 = 12'h32B,
CSR_MHPMEVENT12 = 12'h32C,
CSR_MHPMEVENT13 = 12'h32D,
CSR_MHPMEVENT14 = 12'h32E,
CSR_MHPMEVENT15 = 12'h32F,
CSR_MHPMEVENT16 = 12'h330,
CSR_MHPMEVENT17 = 12'h331,
CSR_MHPMEVENT18 = 12'h332,
CSR_MHPMEVENT19 = 12'h333,
CSR_MHPMEVENT20 = 12'h334,
CSR_MHPMEVENT21 = 12'h335,
CSR_MHPMEVENT22 = 12'h336,
CSR_MHPMEVENT23 = 12'h337,
CSR_MHPMEVENT24 = 12'h338,
CSR_MHPMEVENT25 = 12'h339,
CSR_MHPMEVENT26 = 12'h33A,
CSR_MHPMEVENT27 = 12'h33B,
CSR_MHPMEVENT28 = 12'h33C,
CSR_MHPMEVENT29 = 12'h33D,
CSR_MHPMEVENT30 = 12'h33E,
CSR_MHPMEVENT31 = 12'h33F,
CSR_MCYCLE = 12'hB00,
CSR_MINSTRET = 12'hB02,
CSR_MHPMCOUNTER3 = 12'hB03,
CSR_MHPMCOUNTER4 = 12'hB04,
CSR_MHPMCOUNTER5 = 12'hB05,
CSR_MHPMCOUNTER6 = 12'hB06,
CSR_MHPMCOUNTER7 = 12'hB07,
CSR_MHPMCOUNTER8 = 12'hB08,
CSR_MHPMCOUNTER9 = 12'hB09,
CSR_MHPMCOUNTER10 = 12'hB0A,
CSR_MHPMCOUNTER11 = 12'hB0B,
CSR_MHPMCOUNTER12 = 12'hB0C,
CSR_MHPMCOUNTER13 = 12'hB0D,
CSR_MHPMCOUNTER14 = 12'hB0E,
CSR_MHPMCOUNTER15 = 12'hB0F,
CSR_MHPMCOUNTER16 = 12'hB10,
CSR_MHPMCOUNTER17 = 12'hB11,
CSR_MHPMCOUNTER18 = 12'hB12,
CSR_MHPMCOUNTER19 = 12'hB13,
CSR_MHPMCOUNTER20 = 12'hB14,
CSR_MHPMCOUNTER21 = 12'hB15,
CSR_MHPMCOUNTER22 = 12'hB16,
CSR_MHPMCOUNTER23 = 12'hB17,
CSR_MHPMCOUNTER24 = 12'hB18,
CSR_MHPMCOUNTER25 = 12'hB19,
CSR_MHPMCOUNTER26 = 12'hB1A,
CSR_MHPMCOUNTER27 = 12'hB1B,
CSR_MHPMCOUNTER28 = 12'hB1C,
CSR_MHPMCOUNTER29 = 12'hB1D,
CSR_MHPMCOUNTER30 = 12'hB1E,
CSR_MHPMCOUNTER31 = 12'hB1F,
CSR_MCYCLEH = 12'hB80,
CSR_MINSTRETH = 12'hB82,
CSR_MHPMCOUNTER3H = 12'hB83,
CSR_MHPMCOUNTER4H = 12'hB84,
CSR_MHPMCOUNTER5H = 12'hB85,
CSR_MHPMCOUNTER6H = 12'hB86,
CSR_MHPMCOUNTER7H = 12'hB87,
CSR_MHPMCOUNTER8H = 12'hB88,
CSR_MHPMCOUNTER9H = 12'hB89,
CSR_MHPMCOUNTER10H = 12'hB8A,
CSR_MHPMCOUNTER11H = 12'hB8B,
CSR_MHPMCOUNTER12H = 12'hB8C,
CSR_MHPMCOUNTER13H = 12'hB8D,
CSR_MHPMCOUNTER14H = 12'hB8E,
CSR_MHPMCOUNTER15H = 12'hB8F,
CSR_MHPMCOUNTER16H = 12'hB90,
CSR_MHPMCOUNTER17H = 12'hB91,
CSR_MHPMCOUNTER18H = 12'hB92,
CSR_MHPMCOUNTER19H = 12'hB93,
CSR_MHPMCOUNTER20H = 12'hB94,
CSR_MHPMCOUNTER21H = 12'hB95,
CSR_MHPMCOUNTER22H = 12'hB96,
CSR_MHPMCOUNTER23H = 12'hB97,
CSR_MHPMCOUNTER24H = 12'hB98,
CSR_MHPMCOUNTER25H = 12'hB99,
CSR_MHPMCOUNTER26H = 12'hB9A,
CSR_MHPMCOUNTER27H = 12'hB9B,
CSR_MHPMCOUNTER28H = 12'hB9C,
CSR_MHPMCOUNTER29H = 12'hB9D,
CSR_MHPMCOUNTER30H = 12'hB9E,
CSR_MHPMCOUNTER31H = 12'hB9F
} csr_num_e;
// CSR pmp-related offsets
parameter logic [11:0] CSR_OFF_PMP_CFG = 12'h3A0; // pmp_cfg @ 12'h3a0 - 12'h3a3
parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf
// CSR mhpmcounter-related offsets and mask
parameter logic [11:0] CSR_OFF_MCOUNTER_SETUP = 12'h320; // mcounter_setup @ 12'h323 - 12'h33F
parameter logic [11:0] CSR_OFF_MCOUNTER = 12'hB00; // mcounter @ 12'hB03 - 12'hB1F
parameter logic [11:0] CSR_OFF_MCOUNTERH = 12'hB80; // mcounterh @ 12'hB83 - 12'hB9F
parameter logic [11:0] CSR_MASK_MCOUNTER = 12'hFE0;
// CSR status bits
parameter int unsigned CSR_MSTATUS_MIE_BIT = 3;
parameter int unsigned CSR_MSTATUS_MPIE_BIT = 7;