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[rtl] Update RAM ports inside ibex_top

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This commit updates the RAM ports inside ibex_top to reflect recent
changes introduced with lowRISC/opentitan#23212 (SRAM readback mode).

Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
This commit is contained in:
Pascal Nasahl 2024-05-28 15:59:50 +02:00 • committed by Greg Chadwick
parent 5977d4e3a0
commit 0b0b01006c
2 changed files with 72 additions and 64 deletions
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72
dv/uvm/icache/dv/tb/tb.sv
View file

@ -138,27 +138,29 @@ module tb #(
.EnableParity (0),
.NumAddrScrRounds (NumAddrScrRounds)
) tag_bank (
.clk_i (clk),
.rst_ni (rst_n),
.clk_i (clk),
.rst_ni (rst_n),
.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),
.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),
.req_i (ram_if.ic_tag_req[way]),
.req_i (ram_if.ic_tag_req[way]),
.gnt_o (),
.write_i (ram_if.ic_tag_write),
.addr_i (ram_if.ic_tag_addr),
.wdata_i (ram_if.ic_tag_wdata),
.wmask_i ({TagSizeECC{1'b1}}),
.intg_error_i(1'b0),
.gnt_o (),
.write_i (ram_if.ic_tag_write),
.addr_i (ram_if.ic_tag_addr),
.wdata_i (ram_if.ic_tag_wdata),
.wmask_i ({TagSizeECC{1'b1}}),
.intg_error_i (1'b0),
.rdata_o (ram_if.ic_tag_rdata_in[way]),
.rvalid_o (ram_if.ic_tag_rvalid[way]),
.raddr_o (),
.rerror_o (),
.cfg_i ('0)
.rdata_o (ram_if.ic_tag_rdata_in[way]),
.rvalid_o (ram_if.ic_tag_rvalid[way]),
.raddr_o (),
.rerror_o (),
.cfg_i ('0),
.wr_collision_o (),
.write_pending_o ()
);
// Data RAM instantiation
@ -170,27 +172,29 @@ module tb #(
.ReplicateKeyStream (1),
.NumAddrScrRounds (NumAddrScrRounds)
) data_bank (
.clk_i (clk),
.rst_ni (rst_n),
.clk_i (clk),
.rst_ni (rst_n),
.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),
.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),
.req_i (ram_if.ic_data_req[way]),
.req_i (ram_if.ic_data_req[way]),
.gnt_o (),
.write_i (ram_if.ic_data_write),
.addr_i (ram_if.ic_data_addr),
.wdata_i (ram_if.ic_data_wdata),
.wmask_i ({LineSizeECC{1'b1}}),
.intg_error_i(1'b0),
.gnt_o (),
.write_i (ram_if.ic_data_write),
.addr_i (ram_if.ic_data_addr),
.wdata_i (ram_if.ic_data_wdata),
.wmask_i ({LineSizeECC{1'b1}}),
.intg_error_i (1'b0),
.rdata_o (ram_if.ic_data_rdata_in[way]),
.rvalid_o (ram_if.ic_data_rvalid[way]),
.raddr_o (),
.rerror_o (),
.cfg_i ('0)
.rdata_o (ram_if.ic_data_rdata_in[way]),
.rvalid_o (ram_if.ic_data_rvalid[way]),
.raddr_o (),
.rerror_o (),
.cfg_i ('0),
.wr_collision_o (),
.write_pending_o ()
);
end

64
rtl/ibex_top.sv
View file

@ -571,24 +571,26 @@ module ibex_top import ibex_pkg::*; #(
.clk_i,
.rst_ni,
.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),
.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),
.req_i (ic_tag_req[way]),
.req_i (ic_tag_req[way]),
.gnt_o (),
.write_i (ic_tag_write),
.addr_i (ic_tag_addr),
.wdata_i (ic_tag_wdata),
.wmask_i ({TagSizeECC{1'b1}}),
.intg_error_i(1'b0),
.gnt_o (),
.write_i (ic_tag_write),
.addr_i (ic_tag_addr),
.wdata_i (ic_tag_wdata),
.wmask_i ({TagSizeECC{1'b1}}),
.intg_error_i (1'b0),
.rdata_o (ic_tag_rdata[way]),
.rvalid_o (),
.raddr_o (),
.rerror_o (),
.cfg_i (ram_cfg_i)
.rdata_o (ic_tag_rdata[way]),
.rvalid_o (),
.raddr_o (),
.rerror_o (),
.cfg_i (ram_cfg_i),
.wr_collision_o (),
.write_pending_o ()
);
// Data RAM instantiation
@ -604,24 +606,26 @@ module ibex_top import ibex_pkg::*; #(
.clk_i,
.rst_ni,
.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),
.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),
.req_i (ic_data_req[way]),
.req_i (ic_data_req[way]),
.gnt_o (),
.write_i (ic_data_write),
.addr_i (ic_data_addr),
.wdata_i (ic_data_wdata),
.wmask_i ({LineSizeECC{1'b1}}),
.intg_error_i(1'b0),
.gnt_o (),
.write_i (ic_data_write),
.addr_i (ic_data_addr),
.wdata_i (ic_data_wdata),
.wmask_i ({LineSizeECC{1'b1}}),
.intg_error_i (1'b0),
.rdata_o (ic_data_rdata[way]),
.rvalid_o (),
.raddr_o (),
.rerror_o (),
.cfg_i (ram_cfg_i)
.rdata_o (ic_data_rdata[way]),
.rvalid_o (),
.raddr_o (),
.rerror_o (),
.cfg_i (ram_cfg_i),
.wr_collision_o (),
.write_pending_o ()
);
`ifdef INC_ASSERT