Enable coverage collection and merging for Incisive sims (#552)

Signed-off-by: Udi <udij@google.com>

dv/uvm/Makefile

@@ -153,5 +153,11 @@ fcov:
           --custom_target ${DV_DIR}/riscv_dv_extension \
 
 # Load verdi to review coverage
-cov:
+cov_vcs:
 	cd ${OUT}/rtl_sim; verdi -cov -covdir test.vdb &
+
+cov_ius:
+	if [ ! -d "${OUT}/rtl_sim/cov_work/scope/merged_cov" ]; \
+	  then imc -execcmd "merge -out ${OUT}/rtl_sim/cov_work/scope/merged_cov ${OUT}/rtl_sim/cov_work/scope/test_*"; \
+  	fi
+	imc -load ${OUT}/rtl_sim/cov_work/scope/merged_cov &

dv/uvm/cover.ccf

@@ -0,0 +1,36 @@
+# set ibex_core_tracing as top of coverage tree
+select_coverage -bef -module ibex_core_tracing...
+
+# Toggle coverage should only apply to the top level of DUT
+select_coverage -toggle -module ibex_core_tracing
+
+# Remove the tracer module from all coverage collection
+deselect_coverage -all -module ibex_tracer
+
+# top level toggle coverage only collected for input/output ports
+set_toggle_portsonly
+
+# allow toggle coverage to be collected for SV multidimensional arrays and enums
+set_toggle_scoring -sv_mda -sv_enum
+
+# exclude constants from coverage collection
+set_com
+
+# enables coverage scoring for statements
+set_assign_scoring
+
+# enable coverage score for branches and ternary assignments
+set_branch_scoring
+
+# enable coverage of all operators and continuous/procedural statements
+set_expr_coverable_operators -all
+set_expr_coverable_statements -all
+
+# enable coverage of FSM reset states
+set_fsm_reset_scoring
+
+# disable FSM arc coverage
+set_fsm_arc_scoring -off
+
+# enables coverage for all assertions/covergroups
+select_functional

dv/uvm/sim.py

@@ -112,11 +112,13 @@ def rtl_compile(compile_cmd, test_list, output_dir, lsf_cmd, opts):
     run_cmd(cmd)
 
 
-def rtl_sim(sim_cmd, test_list, output_dir, bin_dir, lsf_cmd, seed, opts):
+def rtl_sim(sim_cmd, simulator, test_list, output_dir, bin_dir,
+            lsf_cmd, seed, opts):
   """Run the instruction generator
 
   Args:
     sim_cmd    : Simulation command
+    simulator  : Simulator being used
     test_list  : List of assembly programs
     output_dir : Simulation output directory
     bin_dir    : Directory of the ELF files
@@ -124,6 +126,12 @@ def rtl_sim(sim_cmd, test_list, output_dir, bin_dir, lsf_cmd, seed, opts):
     seed       : Seed of RTL simulation
     opts       : Simulation options
   """
+  check_return_code = True
+  # Don't check return code for IUS sims, as a failure will short circuit
+  # the entire simulation flow
+  if simulator == "ius":
+    check_return_code = False
+    logging.debug("Disable return code checking for %s simulator" % simulator)
   # Run the RTL simulation
   sim_cmd = re.sub("<out>", output_dir, sim_cmd)
   sim_cmd = re.sub("<sim_opts>", opts, sim_cmd)
@@ -148,12 +156,12 @@ def rtl_sim(sim_cmd, test_list, output_dir, bin_dir, lsf_cmd, seed, opts):
       cmd = re.sub('\n', '', cmd)
       if lsf_cmd == "":
         logging.info("Running %s with %s" % (test['rtl_test'], binary))
-        run_cmd(cmd, 300)
+        run_cmd(cmd, 300, check_return_code = check_return_code)
       else:
         cmd_list.append(cmd)
   if lsf_cmd != "":
     logging.info("Running %0d simulation jobs." % len(cmd_list))
-    run_parallel_cmd(cmd_list, 600)
+    run_parallel_cmd(cmd_list, 600, check_return_code = check_return_code)
 
 
 def compare(test_list, iss, output_dir, verbose):
@@ -276,8 +284,8 @@ if args.steps == "all" or re.match("compile", args.steps):
 
 # Run RTL simulation
 if args.steps == "all" or re.match("sim", args.steps):
-  rtl_sim(sim_cmd, matched_list, output_dir, bin_dir, args.lsf_cmd,
-          args.seed, args.sim_opts)
+  rtl_sim(sim_cmd, args.simulator, matched_list, output_dir, bin_dir,
+          args.lsf_cmd, args.seed, args.sim_opts)
 
 # Compare RTL & ISS simulation result.;
 if args.steps == "all" or re.match("compare", args.steps):

dv/uvm/yaml/rtl_simulation.yaml

@@ -75,10 +75,16 @@
               -sv -uvm -uvmhome CDNS-1.2
               -f ibex_dv.f
               -elaborate -licqueue
-              -l <out>/ius/compile.log"
+              -l <out>/ius/compile.log <cov_opts>"
+    cov_opts: >
+      -coverage all
+      -covfile cover.ccf
   sim:
     cmd: >
-      irun -R -nclibdirpath <out>/ius <sim_opts> -svseed <seed> -licqueue <wave_opts>
+      irun -R -nclibdirpath <out>/ius <sim_opts> -svseed <seed> -licqueue <wave_opts> <cov_opts>
+    cov_opts: >
+      -covoverwrite
+      -covworkdir <out>/cov_work
+      -covbaserun test
     wave_opts: >
       -input <cwd>/ius.tcl
-