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modified data load event

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This commit is contained in:
Pasquale Davide Schiavone 2017-03-27 17:58:05 +02:00
parent 152309fadf
commit 0eba7ea82c
4 changed files with 10 additions and 19 deletions
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5
zeroriscy_controller.sv
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@ -212,7 +212,7 @@ module zeroriscy_controller
end else begin
// no debug request incoming, normal execution flow
if (fetch_enable_i || exc_req)
if (fetch_enable_i || ext_req_i)
begin
ctrl_fsm_ns = FIRST_FETCH;
end
@ -228,7 +228,7 @@ module zeroriscy_controller
end
// handle exceptions
if (exc_req) begin
if (ext_req_i) begin
pc_mux_o = PC_EXCEPTION;
pc_set_o = 1'b1;
exc_ack_o = 1'b1;
@ -250,7 +250,6 @@ module zeroriscy_controller
begin // now analyze the current instruction in the ID stage
is_decoding_o = 1'b1;
unique case (1'b1)
branch_set_i: begin

6
zeroriscy_core.sv
View file

@ -170,11 +170,9 @@ module zeroriscy_core
// stall control
logic halt_if;
logic if_ready;
logic id_ready;
logic ex_ready;
logic if_valid;
logic id_valid;
logic wb_valid;
@ -317,9 +315,7 @@ module zeroriscy_core
// pipeline stalls
.halt_if_i ( halt_if ),
.if_ready_o ( if_ready ),
.id_ready_i ( id_ready ),
.if_valid_o ( if_valid ),
.if_busy_o ( if_busy ),
.perf_imiss_o ( perf_imiss )
@ -374,11 +370,9 @@ module zeroriscy_core
// Stalls
.halt_if_o ( halt_if ),
.if_ready_i ( if_ready ),
.id_ready_o ( id_ready ),
.ex_ready_i ( ex_ready ),
.if_valid_i ( if_valid ),
.id_valid_o ( id_valid ),
.alu_operator_ex_o ( alu_operator_ex ),

4
zeroriscy_id_stage.sv
View file

@ -77,12 +77,10 @@ module zeroriscy_id_stage
// Stalls
output logic halt_if_o, // controller requests a halt of the IF stage
input logic if_ready_i, // IF stage is done
output logic id_ready_o, // ID stage is ready for the next instruction
input logic ex_ready_i,
input logic if_valid_i, // IF stage is done
output logic id_valid_o, // ID stage is done
// ALU
@ -638,7 +636,7 @@ module zeroriscy_id_stage
assign data_wdata_ex_o = regfile_data_rb_id;
assign data_req_ex_o = data_req_id;
assign data_reg_offset_ex_o = data_reg_offset_id;
assign data_load_event_ex_o = ((data_req_id & (~halt_id)) ? data_load_event_id : 1'b0);
assign data_load_event_ex_o = data_load_event_id;
assign alu_operator_ex_o = alu_operator;
assign alu_operand_a_ex_o = alu_operand_a;

14
zeroriscy_if_stage.sv
View file

@ -67,9 +67,9 @@ module zeroriscy_if_stage
input logic [31:0] dbg_jump_addr_i,
// pipeline stall
input logic halt_if_i,
output logic if_ready_o,
input logic id_ready_i,
output logic if_valid_o,
// misc signals
output logic if_busy_o, // is the IF stage busy fetching instructions?
output logic perf_imiss_o // Instruction Fetch Miss
@ -79,7 +79,7 @@ module zeroriscy_if_stage
enum logic[0:0] {WAIT, IDLE } offset_fsm_cs, offset_fsm_ns;
logic valid;
logic if_ready, if_valid;
// prefetch buffer related signals
logic prefetch_busy;
logic branch_req;
@ -188,7 +188,7 @@ module zeroriscy_if_stage
if (fetch_valid) begin
valid = 1'b1; // an instruction is ready for ID stage
if (req_i && if_valid_o) begin
if (req_i && if_valid) begin
fetch_ready = 1'b1;
offset_fsm_ns = WAIT;
end
@ -252,7 +252,7 @@ module zeroriscy_if_stage
else
begin
if (if_valid_o)
if (if_valid)
begin
instr_valid_id_o <= 1'b1;
instr_rdata_id_o <= instr_decompressed;
@ -267,8 +267,8 @@ module zeroriscy_if_stage
end
assign if_ready_o = valid & id_ready_i;
assign if_valid_o = (~halt_if_i) & if_ready_o;
assign if_ready = valid & id_ready_i;
assign if_valid = (~halt_if_i) & if_ready;
//----------------------------------------------------------------------------
// Assertions