FPGA example: add support for the Arty A7-35

Makefile

@@ -7,7 +7,7 @@ help:
 	@echo "or how to set-up the different environments."
 
 # Use a parallel run (make -j N) for a faster build
-build-all: build-riscv-compliance build-simple-system build-arty \
+build-all: build-riscv-compliance build-simple-system build-arty-100 \
       build-csr-test
 
 
@@ -46,9 +46,10 @@ run-simple-system: sw-simple-hello | $(Vibex_simple_system)
 		--raminit=$(simple-system-program)
 
 
-# Arty A7 100T
-# Use the following targets:
-# - "build-arty"
+# Arty A7 FPGA example
+# Use the following targets (depending on your hardware):
+# - "build-arty-35"
+# - "build-arty-100"
 # - "program-arty"
 arty-sw-program = examples/sw/led/led.vmem
 sw-led: $(arty-sw-program)
@@ -57,13 +58,20 @@ sw-led: $(arty-sw-program)
 $(arty-sw-program):
 	cd examples/sw/led && $(MAKE)
 
-build-arty: sw-led
+.PHONY: build-arty-35
+build-arty-35: sw-led
 	fusesoc --cores-root=. run --target=synth --setup --build \
-		lowrisc:ibex:top_artya7_100
+		lowrisc:ibex:top_artya7 --part xc7a35ticsg324-1L
+
+.PHONY: build-arty-100
+build-arty-100: sw-led
+	fusesoc --cores-root=. run --target=synth --setup --build \
+		lowrisc:ibex:top_artya7 --part xc7a100ticsg324-1
 
 .PHONY: program-arty
 program-arty:
-	fusesoc --cores-root=. pgm lowrisc:ibex:top_artya7_100
+	fusesoc --cores-root=. run --target=synth --run \
+		lowrisc:ibex:top_artya7
 
 
 # Lint check

examples/fpga/artya7/README.md

@@ -11,8 +11,26 @@ Please see [examples](https://ibex-core.readthedocs.io/en/latest/examples.html "
   - `fusesoc` and its dependencies
   - Xilinx Vivado
 
+### Hardware
+
+  - Either a Digilent Arty A7-35 oder A7-100 board
+
 ## Build
 
+The easiest way to build and execute this example is to call the following make goals from the root directory.
+
+Use the following for the Arty A7-35
+
+```
+make build-arty-35 program-arty
+```
+
+and for the Arty A7-100
+
+```
+make build-arty-100 program-arty
+```
+
 ### Software
 
 First the software must be built. Go into `examples/sw/led` and call:
@@ -25,14 +43,19 @@ The setting of `CC` is only required if `riscv32-unknown-elf-gcc` is not availab
 The path to the RV32 compiler `/path/to/RISC-V-compiler` depends on the environment.
 For example, it can be for example `/opt/riscv/bin/riscv-none-embed-gcc` if the whole path is required or simply the name of the executable if it is available through the `PATH` environment variable.
 
-This should produce a `led.vmem` file which is used in the synthesises to update the SRAM storage.
+This should produce a `led.vmem` file which is used in the synthesis to update the SRAM storage.
 
 ### Hardware
 
-Run the following command at the top level to build the hardware.
+Run either of the following commands at the top level to build the respective hardware.
+Both variants of the Arty A7 are supported and can be selected via the `--parts` parameter.
 
 ```
-fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7_100
+fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a35ticsg324-1L
+```
+
+```
+fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1
 ```
 
 This will create a directory `build` which contains the output files, including
@@ -43,7 +66,7 @@ the bitstream.
 After the board is connected to the computer it can be programmed with:
 
 ```
-fusesoc --cores-root=. pgm lowrisc:ibex:top_artya7_100
+fusesoc --cores-root=. run --target=synth --run lowrisc:ibex:top_artya7
 ```
 
 LED1/LED3 and LED0/LED2 should alternately be on after the FPGA programming is finished.

examples/fpga/artya7/rtl/top_artya7.sv

@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-module top_artya7_100 (
+module top_artya7 (
     input               IO_CLK,
     input               IO_RST_N,
     output [3:0]        LED

examples/fpga/artya7/top_artya7.core

@@ -2,15 +2,15 @@ CAPI=2:
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:ibex:top_artya7_100:0.1"
-description: "Ibex example toplevel for the Arty A7-100 board"
+name: "lowrisc:ibex:top_artya7:0.1"
+description: "Ibex example toplevel for Arty A7 boards (both, -35 and -100)"
 filesets:
   files_rtl_artya7:
     depend:
       - lowrisc:ibex:ibex_core
       - lowrisc:ibex:fpga_xilinx_shared
     files:
-      - rtl/top_artya7_100.sv
+      - rtl/top_artya7.sv
     file_type: systemVerilogSource
 
   files_constraints:
@@ -37,9 +37,9 @@ targets:
     filesets:
       - files_rtl_artya7
       - files_constraints
-    toplevel: top_artya7_100
+    toplevel: top_artya7
     parameters:
       - SRAM_INIT_FILE
     tools:
       vivado:
-        part: "xc7a100tcsg324-1"  # Arty A7-100
+        part: "xc7a100tcsg324-1"  # Default to Arty A7-100