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only jump once even when there are stalls

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This commit is contained in:
Andreas Traber 2015-12-26 13:30:44 +01:00
parent 1b98c11e12
commit 11ffa5630c
2 changed files with 15 additions and 4 deletions
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11
controller.sv
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@ -116,6 +116,8 @@ module riscv_controller
FLUSH_EX, FLUSH_WB,
DBG_WAIT_BRANCH, DBG_SIGNAL, DBG_WAIT } ctrl_fsm_cs, ctrl_fsm_ns;
logic jump_done, jump_done_q;
logic reg_d_ex_is_reg_a_id;
logic reg_d_ex_is_reg_b_id;
logic reg_d_ex_is_reg_c_id;
@ -161,6 +163,7 @@ module riscv_controller
pc_mux_o = `PC_BOOT;
pc_set_o = 1'b0;
jump_done = jump_done_q;
ctrl_fsm_ns = ctrl_fsm_cs;
@ -245,8 +248,10 @@ module riscv_controller
pc_mux_o = `PC_JUMP;
// if there is a jr stall, wait for it to be gone
if (~jr_stall_o)
if ((~jr_stall_o) && (~jump_done_q)) begin
pc_set_o = 1'b1;
jump_done = 1'b1;
end
// we don't have to change our current state here as the prefetch
// buffer is automatically invalidated, thus the next instruction
@ -506,10 +511,14 @@ module riscv_controller
if ( rst_n == 1'b0 )
begin
ctrl_fsm_cs <= RESET;
jump_done_q <= 1'b0;
end
else
begin
ctrl_fsm_cs <= ctrl_fsm_ns;
// clear when id is valid (no instruction incoming)
jump_done_q <= jump_done & (~id_valid_i);
end
end

6
if_stage.sv
View file

@ -357,8 +357,6 @@ module riscv_if_stage
end
else
begin
if (clear_instr_valid_i)
instr_valid_id_o <= 1'b0;
if (if_valid_o)
begin
@ -371,7 +369,11 @@ module riscv_if_stage
if (fetch_is_hwlp)
hwlp_dec_cnt_id_o <= hwlp_dec_cnt_if;
end else if (clear_instr_valid_i) begin
instr_valid_id_o <= 1'b0;
end
end
end