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Make sure branches are only done once

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This commit is contained in:
Andreas Traber 2015-11-23 16:51:06 +01:00
parent 81a5e04a62
commit 1673d3f62a
2 changed files with 6 additions and 4 deletions
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3
ex_stage.sv
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@ -50,6 +50,7 @@ module riscv_ex_stage
input logic mult_mac_en_i,
// input from ID stage
input logic branch_in_ex_i,
input logic [4:0] regfile_alu_waddr_i,
input logic regfile_alu_we_i,
@ -179,7 +180,7 @@ module riscv_ex_stage
end
end
assign ex_ready_o = lsu_ready_ex_i & wb_ready_i;
assign ex_ready_o = (lsu_ready_ex_i & wb_ready_i) | branch_in_ex_i;
assign ex_valid_o = ex_ready_o;
endmodule

7
riscv_core.sv
View file

@ -462,12 +462,13 @@ module riscv_core
.csr_rdata_i ( csr_rdata ),
// From ID Stage: Regfile control signals
.branch_in_ex_i ( branch_in_ex ),
.regfile_alu_waddr_i ( regfile_alu_waddr_ex ),
.regfile_alu_we_i ( regfile_alu_we_ex ),
.regfile_waddr_i ( regfile_waddr_ex ),
.regfile_we_i ( regfile_we_ex ),
.regfile_alu_we_i ( regfile_alu_we_ex ),
.regfile_alu_waddr_i ( regfile_alu_waddr_ex ),
// Output of ex stage pipeline
.regfile_waddr_wb_o ( regfile_waddr_fw_wb_o ),
.regfile_we_wb_o ( regfile_we_wb ),