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[dv] Add RF signals to core_ibex_dut_probe_if

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Signed-off-by: Andreas Kurth <adk@lowrisc.org>
This commit is contained in:
Andreas Kurth 2022-10-28 20:22:25 +00:00 • committed by Andreas Kurth
parent e9a866ef55
commit 173387e1c7
2 changed files with 23 additions and 10 deletions
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8
dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv vendored
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@ -21,6 +21,10 @@ interface core_ibex_dut_probe_if(input logic clk);
ibex_pkg::ctrl_fsm_e ctrl_fsm_cs;
logic debug_mode;
logic double_fault_seen;
logic rf_ren_a;
logic rf_ren_b;
logic rf_rd_a_wb_match;
logic rf_rd_b_wb_match;
clocking dut_cb @(posedge clk);
output fetch_enable;
@ -40,6 +44,10 @@ interface core_ibex_dut_probe_if(input logic clk);
input ctrl_fsm_cs;
input debug_mode;
input double_fault_seen;
input rf_ren_a;
input rf_ren_b;
input rf_rd_a_wb_match;
input rf_rd_b_wb_match;
endclocking
initial begin

25
dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
View file

@ -200,16 +200,21 @@ module core_ibex_tb_top;
// Irq interface connections
assign irq_vif.reset = ~rst_n;
// Dut_if interface connections
assign dut_if.ecall = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ecall_insn;
assign dut_if.wfi = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.wfi_insn;
assign dut_if.ebreak = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ebrk_insn;
assign dut_if.illegal_instr = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.illegal_insn_d;
assign dut_if.dret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.dret_insn;
assign dut_if.mret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.mret_insn;
assign dut_if.reset = ~rst_n;
assign dut_if.priv_mode = dut.u_ibex_top.u_ibex_core.priv_mode_id;
assign dut_if.ctrl_fsm_cs = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ctrl_fsm_cs;
assign dut_if.debug_mode = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.debug_mode_q;
assign dut_if.ecall = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ecall_insn;
assign dut_if.wfi = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.wfi_insn;
assign dut_if.ebreak = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ebrk_insn;
assign dut_if.illegal_instr
= dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.illegal_insn_d;
assign dut_if.dret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.dret_insn;
assign dut_if.mret = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.mret_insn;
assign dut_if.reset = ~rst_n;
assign dut_if.priv_mode = dut.u_ibex_top.u_ibex_core.priv_mode_id;
assign dut_if.ctrl_fsm_cs = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ctrl_fsm_cs;
assign dut_if.debug_mode = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.debug_mode_q;
assign dut_if.rf_ren_a = dut.u_ibex_top.u_ibex_core.rf_ren_a;
assign dut_if.rf_ren_b = dut.u_ibex_top.u_ibex_core.rf_ren_b;
assign dut_if.rf_rd_a_wb_match = dut.u_ibex_top.u_ibex_core.rf_rd_a_wb_match;
assign dut_if.rf_rd_b_wb_match = dut.u_ibex_top.u_ibex_core.rf_rd_b_wb_match;
// Instruction monitor connections
assign instr_monitor_if.reset = ~rst_n;
assign instr_monitor_if.valid_id = dut.u_ibex_top.u_ibex_core.id_stage_i.instr_valid_i;