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Modify control in branch case

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This commit is contained in:
Markus Wegmann 2017-01-09 18:41:26 +01:00
parent 4a79c9f280
commit 18000c5b90
2 changed files with 23 additions and 15 deletions
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23
controller.sv
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@ -354,6 +354,7 @@ module riscv_controller
// CONFIG_REGION: NO_JUMP_ADDER
`ifdef NO_JUMP_ADDER
halt_if_o = 1'b1;
halt_id_o = 1'b1;
ctrl_fsm_ns = WAIT_BRANCH_EX;
`else
// there is a branch in the EX stage that is taken
@ -443,18 +444,26 @@ module riscv_controller
// make sure the current instruction has been executed
// before changing state to non-decode
if (id_ready_i) begin
if ((jump_in_id_i == BRANCH_COND) & branch_taken_ex_i & id_ready_i)
// CONFIG_REGION: NO_JUMP_ADDER
`ifdef NO_JUMP_ADDER
if ((jump_in_id_i == BRANCH_COND) & branch_taken_ex_i)
begin
// CONFIG_REGION: NO_JUMP_ADDER
`ifdef NO_JUMP_ADDER
ctrl_fsm_ns = WAIT_BRANCH_EX;
`else
pc_mux_o = PC_BRANCH;
pc_set_o = 1'b1;
`endif
end
else
ctrl_fsm_ns = DBG_SIGNAL;
`else
if ((jump_in_id_i == BRANCH_COND) & branch_taken_ex_i)
begin
pc_mux_o = PC_BRANCH;
pc_set_o = 1'b1;
end
ctrl_fsm_ns = DBG_SIGNAL;
`endif
end
end
end

15
id_stage.sv
View file

@ -1748,19 +1748,18 @@ module riscv_id_stage
alu_operand_b_ex_o = alu_operand_b;
alu_operand_c_ex_o = alu_operand_c;
regfile_we_ex_o = (regfile_we_id & ~halt_id);
regfile_alu_we_ex_o = (regfile_alu_we_id & ~halt_id);
regfile_we_ex_o = (regfile_we_id & (~halt_id));
regfile_alu_we_ex_o = (regfile_alu_we_id & (~halt_id));
csr_access_ex_o = (csr_access & ~halt_id);
csr_access_ex_o = csr_access;
csr_op_ex_o = csr_op;
data_req_ex_o = (data_req_id & ~halt_id);
data_req_ex_o = data_req_id;
// CONFIG_REGION: ONLY_ALIGNED
`ifndef ONLY_ALIGNED
data_reg_offset_ex_o = data_reg_offset_id;
`endif // ONLY_ALIGNED
data_load_event_ex_o = ((data_req_id & ~halt_id) ? data_load_event_id : 1'b0);
data_load_event_ex_o = ((data_req_id & (~halt_id)) ? data_load_event_id : 1'b0);
// CONFIG_REGION: ONLY_ALIGNED
`ifndef ONLY_ALIGNED
@ -1768,7 +1767,7 @@ module riscv_id_stage
`endif // ONLY_ALIGNED
pc_ex_o = pc_id_i;
branch_in_ex_o = (jump_in_dec == BRANCH_COND);
branch_in_ex_o = (jump_in_id == BRANCH_COND);
// CONFIG_REGION: NO_JUMP_ADDER
`ifdef NO_JUMP_ADDER
jal_in_ex_o = ((jump_in_id == BRANCH_JALR) || (jump_in_id == BRANCH_JAL));
@ -1781,7 +1780,7 @@ module riscv_id_stage
// stall control
// CONFIG_REGION: ONLY_ALIGNED
`ifndef ONLY_ALIGNED
`ifdef ONLY_ALIGNED
assign id_ready_o = ((~misaligned_stall) & (~jr_stall) & (~load_stall) & ex_ready_i);
`else
assign id_ready_o = ((~jr_stall) & (~load_stall) & ex_ready_i);